• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.963-966
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• 2003

This paper proposes a new locking algorithm of the delay locked loop (DLL) which reduces the lock-acquisition time and eliminates false locking problem to enlarge the operating frequency range. The proposed DLL uses the modified phase frequency detector (MPFD) and the modified charge pump (MCP) to avoid the false locking problem. Adopting a new lock detector that measures delay between elects helps the fast lock-acquisition time greatly. The idea has been confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.9C
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• pp.581-588
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• 2011

In this paper, we propose a novel unambiguous code tracking scheme for cosine phased binary offset carrier (BOC) signals. We first obtain the sub-correlation functions composing the BOC autocorrelation function, and then, re-combine the sub-correlation functions generating a correlation function with no side-peak. Finally, by using the correlation function with no side-peak in the delay lock loop, the proposed scheme performs unambiguous signal tracking. Numerical results demonstrate that the proposed scheme provides a performance improvement over the conventional unambiguous scheme in terms of the tracking error standard deviation (TESD).

• Proceedings of the Korean Information Science Society Conference
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• 2011.06a
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• pp.559-561
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• 2011

멀티코어 환경에서는 공유 데이터에 대한 동기화로 인한 병목 현상이 중요한 문제점 중의 하나이다. 그리고 동적 메모리 할당자는 대량의 메모리를 할당 및 해제하는 프로그램에서 공유 데이터에 대한 동기화 문제로 성능 저하를 유발시키고 있다. 이를 해결하기 위해 다양한 lock-free 메모리 할당 기법들이 소개되었지만 false sharing과 heap blow-up과 같은 여러 가지 문제점들을 가지고 있다. 이에 본 논문에서는 새로운 연속할당 기법을 제안하고, 이를 이용하여 동일 블록 내의 오브젝트 할당/해제에 따른 동기화 문제를 해결함으로써 효과적인 lock-free 메모리 할당 기법을 제안하였다. 그리고 제안 기법을 구현하여 기존의 메모리 할당 기법들과 실험을 통하여 검증하였으며, 대량의 메모리를 사용하는 멀티 스레드 환경에서 특히 좋은 성능을 보이는 것을 확인하였다.

• Journal of Positioning, Navigation, and Timing
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• v.4 no.3
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• pp.107-114
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• 2015

Binary Offset Carrier (BOC) signal planned for future Global Navigation Satellite System (GNSS) provided better positioning accuracy and smaller multipath error than GPS C/A signal. However, due to the multiple side peaks in the auto-correlation function (ACF) of the BOC modulated signals, a receiver may false lock onto one of the side peaks in the tracking mode. This false lock would then result in a fatal tracking error. In this paper, we propose an unambiguous tracking method for composite BOC (CBOC) signals to mitigate this problem. It aims to reduce the side peaks of the ACF of CBOC modulated signals. It is based on the combination of traditional CBOC correlation function (CF) and reference CF of unmodulated pseudo- random noise code (PRN code). First, we present that cross-correlation function (CCF) with unmodulated PRN code is close to the secondary peaks of the traditional CBOC. Then, we obtain an unambiguous correlation function by subtracting traditional CBOC ACF from these CFs. Finally, the tracking performance for the CBOC signals is examined, and it is shown that the proposed method has better performance than the traditional unambiguous tracking method in additive white Gaussian noise (AWGN) channel.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.2
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• pp.13-18
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• 1984

The probability distribution of hold-in time and that of the time to reject false lock are investigated for the tracking procedure in spread spectrum communication systems. These are helpful in deciding dwell time and threshold level of correlatoi circuits. The probability distributions are derived by series expansion of generating function for discrete probability function and summation of the coefficients for corresponding terms. And the formulas described by general system parameters are obtained.

• Journal of the Korean Institute of Telematics and Electronics
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• v.19 no.2
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• pp.38-50
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• 1982

A new type of digital phase-locked loop (DPLL) called the modified digital Costas loop is proposed and analyzed. The main feature of the proposed loop is that the phase error detector of the loop has linear characteristic. This results from the use of the tan-1 (.) function in the loop. Accordingly, the DPLL can be characterized by a modulo-2$\pi$ linear difference equation. This paper is diveide into two parts. In Part I we describe the proposed system, and analyze the performance of the first-and second-order loops in the absence of noise by the Phase Plane technique. The locking ranges for the DPLL's to achieve exact locking independently of initial conditions have been obtained in closed forms. Also, the false lock and oscillation phenomena occurring under some initial conditions have been considered. These results have been verified by computer simulation. In Part ll we analyze the proposed system in the presence of noise. The steady state probability density function, mean and variance of the phase error have been obtained by solving the Chapman-Kolmogorov equation. These results will be presented in Part ll.

• Journal of Information Processing Systems
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• v.14 no.2
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• pp.499-509
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• 2018

Recently, hybrid transactional memory (HyTM) has gained much interest from researchers because it combines the advantages of hardware transactional memory (HTM) and software transactional memory (STM). To provide the concurrency control of transactions, the existing HyTM-based studies use a bloom filter. However, they fail to overcome the typical false positive errors of a bloom filter. Though the existing studies use a global lock, the efficiency of global lock-based memory allocation is significantly low in multi-core environment. In this paper, we propose an efficient hybrid transactional memory scheme using near-optimal retry computation and sophisticated memory management in order to efficiently process transactions in multi-core environment. First, we propose a near-optimal retry computation algorithm that provides an efficient HTM configuration using machine learning algorithms, according to the characteristic of a given workload. Second, we provide an efficient concurrency control for transactions in different environments by using a sophisticated bloom filter. Third, we propose a memory management scheme being optimized for the CPU cache line, in order to provide a fast transaction processing. Finally, it is shown from our performance evaluation that our HyTM scheme achieves up to 2.5 times better performance by using the Stanford transactional applications for multi-processing (STAMP) benchmarks than the state-of-the-art algorithms.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.694-701
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• 2011

This paper addresses a synchronization technique based on an adaptive combining of the sub-correlation functions obtained from multiband sine phased binary offset carrier (BOC) signals, allowing a BOC signal receiver to deal with multiband sine phased BOC signals. Specifically, we first obtain the sub-correlation functions composing the BOC autocorrelation function, and then, re-combine the sub-correlation functions generating a correlation function with no side-peak. Finally, by replacing the BOC autocorrelation with the correlation function with no side-peak in the delay lock loop, the proposed scheme performs unambiguous signal tracking. The proposed synchronization scheme is applicable to generic sine phased BOC signals. Numerical results demonstrate that the proposed scheme provides a performance improvement over the conventional unambiguous schemes in terms of the tracking error standard deviation.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• Journal of IKEEE
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• v.22 no.3
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• pp.723-728
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• 2018

This paper proposes a signal detection method for IoT door lock system which is a new application field of VLC (Visible Light Communication). This paper describes the signal detection technique for user recognition that needs to be overcome in order to apply VLC to door lock system which has a demand for new technology due to security issue. This system has security and high signal detection characteristics because it uses existing infrastructure to communicate with visible light. In order to detect the signal using FFT, the signal of the user who accesses the authentication channel based on the pilot signal is detected, and the performance of the false alarm probability and detection probability is shown in the channel model.