• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.407-410
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• 2012

Recently, wireless network services are widely used, depending on the development of wireless network module technologies and the utilization gradually expanded, and thus is a trend that appears a lot of IT convergence industries. For this study, the OBD-II communication to Import your vehicle information, and other external devices in high-speed driving condition of the vehicle to verify the information system was developed to transfer data to an external server. From various sensors inside the vehicle using the OBD-II connector easily convert all users to read the information, then, Sent to the external server using the wireless network module, high-speed vehicle status check system was implemented. It was to test the performance of the system was developed using the actual circuit in a high-speed road racing vehicles. Transfer data generated from high-speed driving vehicles through the OBD-II scanner and check the status of a high-speed vehicle system was confirmed that this data is normally received. In the future, these new cars convergence of IT technology will grow as a new field of research.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.598-609
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• 2003

This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

• Journal of IKEEE
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• v.23 no.3
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• pp.1092-1095
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• 2019

In this paper, we propose the development of an embedded board for construction of smart factory. The proposed embedded board for construction of smart factory consists of main module, ADC module, I/O module. Main module is a main calculating device which includes communication pard that allows interface with external device with using industrial protocol and is ported operating system makes board operating into. ADC module takes part in transferring digital signal has converted from electrical signal to the main module from the external sensor which is installed on the field. I/O module is an input and output module which transfers to the main module about a status, alarm, command signal of field device and it has a function that blocks external noises from field device with isolation circuit into it. In order to evaluate the performance of the proposed embedded board for construction of smart factory, it has been tested by an authorized testing institute. As a result, quantity of interacting protocol was 5, speed of hardware clock synchronization was under 10us and operating time of battery without source power was over 8 hours. It produced the same result as the world's highest level.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.6 s.348
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• pp.53-61
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• 2006

In high speed flash type or pipelining type A/D Converter, the faster sampling frequency is, the more the effect of DC reference fluctuation is increased by clock feed-through and kick-back. When we measure A/D Converter, further, external noise increases reference voltage fluctuation. Thus reference fluctuation reduction circuit must be needed in high speed A/D converter. Conventional circuit simply uses capacitor but layout area is large and it's not efficient. In this paper, a reference fluctuation reduction circuit using transmission gate is proposed. In order to verify the proposed technique, we designed and manufactured 6bit 2GSPS CMOS A/D converter. The A/D converter is based on 0.18um 1-poly 5-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply. It occupies chip area of $977um\times1040um$. Experimental result shows that SNDR is 36.25 dB and INL/DNL ${\pm}0.5LSB$ when sampling frequency is 2GHz.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.9
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• pp.21-26
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• 2016

This paper presents a step-down DC-DC buck converter with a CCM/DCM dual-mode function for the internal power stage of portable electronic device. The proposed converter that is operated with a high frequency of 1 MHz consists of a power stage and a control block. The power stage has a power MOS transistor, inductor, capacitor, and feedback resistors for the control loop. The control part has a pulse width modulation (PWM) block, error amplifier, ramp generator, and oscillator. In this paper, an external capacitor for compensation has been replaced with a multiplier equivalent CMOS circuit for area reduction of integrated circuits. In addition, the circuit includes protection block, such as over voltage protection (OVP), under voltage lock out (UVLO), and thermal shutdown (TSD) block. The proposed circuit was designed and verified using a $0.18{\mu}m$ CMOS process parameter by Cadence Spectra circuit design program. The SPICE simulation results showed a peak efficiency of 94.8 %, a ripple voltage of 3.29 mV ripple, and a 1.8 V output voltage with supply voltages ranging from 2.7 to 3.3 V.

• Korean Journal of Optics and Photonics
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• v.11 no.6
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• pp.400-404
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• 2000

All-optical clock recovery from a 10 Gb/s RZ signal has been demonstrated using an actively mode-locked figure-eight laser incorporating a semiconductor optical amplifier in the loop-mirror scheme. Optical pulses with 10 ps pulse width were modulated by a LiNb03 external modulator at $2^{23}-1$ PRES and injected into the clock recovery circuit to extract optical pulses with 12 ps width. Regeneration of the original bit pattern has been accomplished by modulating the recovered clock with the same modulator, and no power penalty was observed at $10^{11}$..

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.921-926
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• 2003

This paper describes a new type of the spatial filter detector (SFD) with variable and multi-valued weighting function. This SFD called variable spatial filter detector with multi-valued weighting function (VSFDwMWF) uses current-mode circuits for noise resistance and high-resolution weighting values. Total weighting values consist of 7bit, 6-signal bit and 1-sign bit. We fabricate VSFDwMWF chip using Rohm 0.35${\mu}$m CMOS process. VSFDwMWF chip includes two-dimensional 10${\times}$13 photodiode array and current-mode weighting control circuit. Simulation shows the weighting values are varied and multi-valued by external switching operation. The layout of VSFDwMWF chip is shown.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.883-884
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• 2004

High-speed IC for time-division multiplexing (TDM) optical transmission systems have been designed and fabricated by using InP heterojunction-bipolar-transistor (HBT) technology. The driver IC was developed for driving external modulators, featuring differential outputs and the operation speed up to 10 Gbps with an output voltage swing of 1.3 Vpp at each output which was the limit of the measurement. Because -3 dB frequency was 20GHz, this circuit will be operated up to 20Gbps. 1.3Vpp differential output was achieved by switching 50 mA into a 50 $\Omega$ load. The power dissipation of the driver IC was 1W using a single supply voltage of -3.5Y. Input md output return loss of the IC were better than 10 dB and 15 dB, respectively, from DC to 20GHz. The chip size of fabricated IC was $1.7{\Box}1.2 mm^{2}$.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.557-560
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• 2004

In this study, we design the one-chip PWM IC for SMPS (Switching Mode Power Supply) application. We determine the IC spec. and simulated each block of PWM IC (Reference, Error amp., Comparator, Oscillator) with Smart Spice (SILVACO Circuit Simulation Tool). Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain (${\simeq}65dB$), unity frequency (${\simeq}190kHz$) and large PM($75^{\circ}$).Saw tooth generators operate with 20K oscillation frequency (external resistor, capacitor).

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.865-868
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• 2005

This paper presents a Clock-gating technique that reduces power dissipation of the sequential circuits in the system. The Master Clock of a Clock-gating technique is formed by a quaternary variable. It uses the covering relationship between the triggering transition of the clock and the active cycles of various flip-flops to generate a slave clock for each flip-flop in the circuit. At current RTL designs flip-flop is acted by Master clock's triggering but the Slave Clock of Clock-gating technique doesn't occur trigger when external input conditions have not matched with a condition of logic table. We have applied our clocking technique to UART controller of 8bit microprocess