• Proceedings of the KIEE Conference
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• 2008.04c
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• pp.215-217
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• 2008

This paper describes development of hardware simulator for the PMSG wind power system, which was designed considering wind characteristic, blade characteristic and blade inertia compensation. The simulator generates torque and speed signals for a specific wind turbine with respect to given wind speed. This torque and speed signals are scaled down to fit the input of 2kW PMSG. The PMSG-side converter operates to track the maximum power point, and the grid-side inverter controls the active and reactive power supplied to the grid. The operational feasibility was verified by computer simulations with PSCAD/EMTDC, and the implementation feasibility was confirmed through experimental works with a hardware set-up.

• Proceedings of the KIPE Conference
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• 2009.11a
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• pp.185-187
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• 2009

This paper describes development of a hardware simulator for the PMSG wind power system. The simulator consists of a realistic wind turbine model using anemometer, vector drive, induction motor. The turbine model generates torque and speed signals for a specific wind turbine with real wind speed. The torque and speed signals are scaled down to fit for the input power of 3kW PMSG. The hardware simulator was developed through computer simulations, and the operation was confirmed by experimental works.

• Journal of information and communication convergence engineering
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• v.8 no.5
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• pp.570-574
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• 2010

A thinning algorithm changes a binary fingerprint image to one pixel width. A thinning stage occupies 40% cycle of 32-bit RISC microprocessor system for a fingerprint identification algorithm. Hardware block processing is more effective than software one in speed, because a thinning algorithm is iteration of simple instructions. This paper describes an effective hardware scheme for thinning stage processing using the Verilog-HDL in $160\times192$ Pixel Array. The ZS algorithm was applied for a thinning stage. The hardware scheme was designed and simulated in RTL. The logic was also synthesized by XST in FPGA environment. Experimental results show the performance of the proposed scheme.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.116-124
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• 1994

This paper describes the design of a high-level synthesis system. ISyn: Interface Synthesis System for ISPS-A. which generates hardware satisfying timing constraints. The original version of ISPS is extended to be used for the description/capture of interface operations and timing constraints in the ISPS-A. To generate the schedule satisfying interface constraints the scheduling process is divided into two steps:pre-scheduling and post-scheduling. ISyn allocates hardware modules with I/O ports by the clique partitioning algorithm. Experimental results show that ISyn is capable of synthesizing hardware modules effectively for internal and/or interactive operations.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.616-619
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• 2002

The z-map structure is widely used for NC tool path verification as it is very simple and fast in calculation of Boolean operations. However, if the number of the x-y grid points in a z-map is increased to enhance its accuracy, the computation time for NC verification increases rapidly. To reduce this computation time, we proposed a NC verification method using 3-D graphic acceleration hardwares. In this method, the z-map of the resultant workpiece machined by a NC program is obtained by rendering tool swept volumes along tool pathos and reading the depth buffer of the graphic card. The experimental results show that this hardware-based method is faster than the conventional software-based method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.16 no.12S
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• pp.1210-1216
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• 2003

Recently, as the road capacity reaches the limit and environmental problems becomes serious, there is gradually increased a need for railroad vehicles that are environment-friendly and have time regularity, reliability, and safety. Accordingly, in addition to conventional railroad vehicles, lots of vehicles are being newly developed. We developed the hardware and software of the measurement system for on-line test and evaluation of korean high speed train. The software controls the hardware of the measurement system and acts as interface between users and the system hardware. In this paper, practical experiment are performed to verify mechanical performance of motor and main transformer for Korean high speed rail. The experimental test carried out by using new temperature measurement method and verify the temperature performance of motor and transformer is verified.

• Proceedings of the KIEE Conference
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• 2003.07c
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• pp.1487-1489
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• 2003

For this research, we developed the hardware and software of the measurement system for on-line test and evaluation. The software controls the hardware of the mesurement data and acts as interface between users and the system hardware. In this paper, practical experiment is performed to verify temperature characteristics of induction motor for high speed rail. The experimental test carried out new temperature measurement method. Through this test, temperature characteristics of induction motor is verified.

• Proceedings of the KIPE Conference
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• 2010.11a
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• pp.248-249
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• 2010

This paper describes development of hardware simulator for the PMSG(Permanent Magnet Synchronous Generator) wind power system, which was designed using real wind data. The simulator consists of a realistic wind turbine model using anemometer, vector drive, induction motor. The turbine simulator generates torque and speed signals for a specific wind turbine with respect to given wind speed. This torque and speed signals are scaled down to fit the input of 3kW PMSG. The PMSG-side converter operates to track the maximum power point and the grid-side inverter controls the active and reactive power supplied to the grid. The operational feasibility was first verified by computer simulations with PSCAD/EMTDC. The feasibility of real system implementation was confirmed through experimental works with a hardware set-up.

• Journal of Power Electronics
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• v.11 no.2
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• pp.202-210
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• 2011

Polymer electrolyte membrane (PEM) fuel cell is one of the popular renewable energy sources and widely used in commercial medium power areas from portable electronic devices to electric vehicles. In addition, the increased integration of the PEM fuel cell with power electronics, dynamic loads, and control systems requires accurate electrical models and simulation methods to emulate their electrical behaviors. Advancement in parallel computation techniques, various real-time simulation tools, and smart power hardware have allowed the prototyping of novel apparatus to be investigated in a virtual system under a wide range of realistic conditions repeatedly, safely, and economically. This paper builds up advancements of optimized model constructions for a fuel cell stack system on a real-time simulator in the view points of improving dynamic model accuracy and boosting computation speed. In addition, several considerations for a power hardware-in-the-loop (PHIL) simulation are provided to electrically emulate the PEM fuel cell stack system with power facilities. The effectiveness of the proposed PHIL simulation method developed on Opal RT's RT-Lab Matlab/Simulink based real-time engineering simulator and a programmable power supply is verified using experimental results of the proposed PHIL simulation system with a Ballard Nexa fuel cell stack.

• Transactions of the Korean Society of Mechanical Engineers
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• v.12 no.5
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• pp.968-975
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• 1988

The maximum feedrate generated from the hardware DDA is closely related to its calculation efficiency. The smaller interpolation span results in the lower calculation efficiency. This paper presents the method to improve the calculation efficiency for the smaller interpolation span. For the linear interpolation the higher calculation efficiency can be achieved by putting biggest value that the interpolation DDA can hold. for the circular interpolation, however, the scheme used for linear interpolation does not work since arbitrary change of value in the interpolation DDA changes the radius of the circle. The bit length of the hardware DDA is adjusted instead of adjusting the value in DDA, which results in the every same effect on calculation efficiency for the circular interpolation. The hardware circuit and supporting software are designed, and tested by two axis step motor driven milling machine. The experimental results show that the proposed method drastically increases the maximum feedrate even for the smaller interpolation span.