• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.610-618
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• 2003

Recently, many deterministic built-in self-test schemes to reduce test time have been researched. These schemes can achieve a good quality test by shortening the whole test process, but require complex algorithms or much hardware. In this paper, a new deterministic BIST scheme is provided that reduces the additional hardware requirements, as well as keeping test time to a minimum. The proposed BIST (Built-In Self-Test) methodology brings about the reduction of the hardware requirements for pseudo-random tests as well. Theoretical study demonstrates the possibility of reducing the hardware requirements for both pseudo-random and deterministic tests, with some explanations and examples. Experimental results show that in the proposed test scheme the hardware requirements for the pseudo-random test and deterministic test are less than in previous research.

• Journal of Software Assessment and Valuation
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• v.15 no.2
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• pp.95-100
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• 2019

In this paper, we propose a simple hardware reporting method for errors in soft-RAID systems of Linux OS. Compared with other reporting methods, the proposed method displays error status intuitively without any additional access process such as log-in process or home-page access. In particular, the server actively displays the error status, so the administrator can take immediate action. In order to confirm the effectiveness of the proposed method, the experimental circuit was constructed and the experimental results showed that the error was actively displayed when an error occurred in the storage device. As such, a soft-RAID system can perform almost the same function as a hardware RAID system, thereby ensuring server data reliability at low cost.

• Journal of the Korean Society for Precision Engineering
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• v.1 no.2
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• pp.69-74
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• 1984

In this paper we present a microprocessor-based interpolator using algebraic arithmetic method. The interpolator consists of 2910 "bit-slice" microprocessor chips and 0.5K ROMs of microprogram memory. The system design is an instruction-data-based architecture with 250ns cycle time. A significant feature of the interpolator is that it has flexibility, very fast interpolatioon speed of (max) 250K pulses/sec, and performs additional functions simultaneously. Throughout the paper detailed explanations are given as to how one can design the hardware and software of the interpolator efficently. In addi- tion to hardware and software design, experimental results are pressented.ressented.

• ETRI Journal
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• v.31 no.3
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• pp.339-341
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• 2009

Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.

• Journal of IKEEE
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• v.12 no.2
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• pp.75-80
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• 2008

There are many researches to reduce power consumption of battery-operated Transceiver for 2.4 GHz smartRF applications. However, components such as processor, memory and LCD based power managements reach the limit of reducing power consumption. To overcome the limit, this research proposes novel low-power Transceiver and transceiver Hardware Design. Experimental results in the real smartRF Transceiver show that the proposed methods can reduce power consumption additionally than component based power managements.

• Proceedings of the KIEE Conference
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• 2005.10a
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• pp.122-127
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• 2005

This paper proposes a prototype IED hardware design and it's real-time experimental results. To evaluate performance of the IED, the study is well constructed power system model including power transformer utilizing the EMTP software and the testing is made through simulation of various cases. The relaying that is well constructed using DSP chip and RISC CPU etc. has been developed and the prototype IED has been verified through on-line testing by LabVIEW simulator. The results show that an advanced relaying based prototype IED never mis-operated.

• Journal of Power Electronics
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• v.12 no.2
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• pp.285-293
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• 2012

Multilevel inverters have gained attention in high-power applications due to their numerous advantages in comparison with conventional two-level inverters. In this paper a simplified Space-Vector Modulation (SVM) algorithm for a three-level Neutral-Point Clamped (NPC) inverter is implemented on a Freescale$^{(R)}$ DSP56F8037. The algorithm is based on a simplification of the space-vector diagram for a three-level inverter so that it can be used with a two-level inverter. Once the simplification has been achieved, calculation of the dwell times and the switching sequences are carried out in the same way as for the two-level SVM method. Details of the hardware design are included. Experimental results are analyzed to validate the performance of the simplified algorithm.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.37 no.4
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• pp.154-161
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• 2014

In this research we investigate motion controller performance for mobile robots according to changes in the control loop sampling time. As a result, we suggest a proper range of the sample time, which can minimize final posture errors while improving tracking capability of the controller. For controller implementation into real mobile robots, we use a smooth and continuous motion controller, which can respect robot's path curvature limitation. We examine motion control performance in experimental tests while changing the control loop sampling time. Toward this goal, we compare and analyze experimental results using two different mobile robot platforms; one with real-time control and powerful hardware capability and the other with non-real-time control and limited hardware capability.

• ETRI Journal
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• v.26 no.6
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• pp.535-544
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• 2004

With video compression standards such as MPEG-4, a transmission error happens in a video-packet basis, rather than in a macroblock basis. In this context, we propose a semantic error prioritization method that determines the size of a video packet based on the importance of its contents. A video packet length is made to be short for an important area such as a facial area in order to reduce the possibility of error accumulation. To facilitate the semantic error prioritization, an efficient hardware algorithm for face tracking is proposed. The increase of hardware complexity is minimal because a motion estimation engine is efficiently re-used for face tracking. Experimental results demonstrate that the facial area is well protected with the proposed scheme.

• Smart Structures and Systems
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• v.16 no.6
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• pp.1147-1167
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• 2015

Wireless smart sensors, which have become popular for monitoring applications, are an attractive option for implementing structural control systems, due to their onboard sensing, processing, and communication capabilities. However, wireless smart sensors pose inherent challenges for control, including delays from communication, acquisition hardware, and processing time. Previous research in wireless control, which focused on semi-active systems, has found that sampling rate along with time delays can significantly impact control performance. However, because semi-active systems are guaranteed stable, these issues are typically neglected in the control design. This work achieves active control with smart sensors in an experimental setting. Because active systems are not inherently stable, all the elements of the control loop must be addressed, including data acquisition hardware, processing performance, and control design at slow sampling rates. The sensing hardware is shown to have a significant impact on the control design and performance. Ultimately, the smart sensor active control system achieves comparable performance to the traditional tethered system.