• Journal of the Korean Society for Precision Engineering
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• v.18 no.4
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• pp.167-175
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• 2001

This paper presents design of active roll controller of a vehicle and experimental study using the electric actuating roll control system. Firstly, parameter sensitivity analysis is performed based on 3DOF linear vehicle model. The controller is designed in the frame work of gain-scheduled H$\infty$ control scheme considering the varying parameters induced by laden and running vehicle condition. In order to investigate a feasibility of an active control system, experimental work is performed using hardware-in-the -loop setup which has been constructed by the devised electric actuating system and the full vehicle model with tire characteristics. The performance is evaluated by experiment using hardware-in-the -loop simulation under the conditions of some steer maneuvers and parameter variations.

• Journal of IKEEE
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• v.15 no.1
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• pp.10-14
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• 2011

In this paper, we present an efficient hardware architecture of unrolling image mapper of catadioptric omnidirectional imaging systems. The catadioptric omnidirectional imaging systems generate images of 360 degrees of view and need to be transformed into panorama images in rectangular coordinate. In most application, it has to perform the panorama unrolling in real-time and at low-cost, especially for high-resolution images. The proposed hardware architecture adopts a software/hardware cooperative structure and employs several optimization schemes using look-up-table(LUT) of coordinate conversion. To avoid the on-line division operation caused by the coordinate transformation algorithm, the proposed architecture has the LUT which has pre-computed division factors. And then, the amount of memory used by the LUT is reduced to 1/4 by using symmetrical characteristic compared with the conventional architecture. Experimental results show that the proposed hardware architecture achieves an effective real-time performance and lower implementation cost, and it can be applied to other kinds of catadioptric omnidirectional imaging systems.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1107-1112
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• 1996

A semi-active suspension system with continuously variable damper is greatly expected to be mainly used in the future as a high-performance suspension system due to its cost-effectiveness, light weight, and low energy consumption. To develop the suitable control logic for the semi-active suspension system, the hardware-in-the-loop simulation is performed with the experimental continuously variable damper combined with a quarter-car model. The hardware-in-the-loop simulation results are compared for passive, on/off controlled, and continuously controlled dampers in the aspects of ride comfort and driving safety, assuming each damper to be installed on a vehicle.

• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.11 no.4
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• pp.251-258
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• 1986

There is much redundancy in image data such as TV signals and many techniques to redice it have been studied. In this paper, Hadamard transform is studied through computer simulation and experimental model. Each element of hadamard matrix is either +1 or -1, and the row vectors are orthogonal to another. Its hardware implementation is the simplest of the usual orthogonal transforms because addition and sulbraction are necessary to calculate transformed signals, while not only addition but multiplication are necessary in digital Fourier transform, etc. Linclon data (64$ imes$64) are simulated using 8th-order and 16th-order Hadamard transform, and 8th-order is implemented to hardware. Theoretical calculation and experimental result of 8th-order show that 2.0 bits/sample are required for good quality.

• Journal of Korea Multimedia Society
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• v.4 no.1
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• pp.82-90
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• 2001

Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. This paper proposes a new type of embedded one chip computer fort Hardware Implementation of Genetic Algorithm. The proposed embedded one chip computer consists of 16 Bit CPU care and hardware of genetic algorithm. In contrast to conventional hardware oriented GA which is dependent on main computer in the process of GA, the proposed embedded one chip computer is independent on main computer. Conventional hardware GA uses the fixed length of chromosome but the proposed embedded one chip computer uses the variable length of chromosome by employing the efficient 16 bit Pipeline Unit. Experimental results show that the proposed one chip computer is applicable to the design of evolvable hardware for Random NRZ bit synchronization circuit.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.466-468
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fired length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine

• ETRI Journal
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• v.33 no.4
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• pp.611-620
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• 2011

Since card-type one-time password (OTP) generators became available, power and area consumption has been one of the main issues of hardware OTPs. Because relatively smaller batteries and smaller chip areas are available for this type of OTP compared to existing token-type OTPs, it is necessary to implement power-efficient and compact dedicated OTP hardware modules. In this paper, we design and implement a low-power small-area hardware OTP generator based on the Advanced Encryption Standard (AES). First, we implement a prototype AES hardware module using a 350 nm process to verify the effectiveness of our optimization techniques for the SubBytes transform and data storage. Next, we apply the optimized AES to a real-world OTP hardware module which is implemented using a 180 nm process. Our experimental results show the power consumption of our OTP module using the new AES implementation is only 49.4% and 15.0% of those of an HOTP and software-based OTP, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.718-723
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• 2002

This paper proposes a new type of evolvable hardware for implementing the clone of Moore State machine. The proposed Evolvable Hardware is employed efficient pipeline parallelization, handshaking mechanism and fitness function in FPGA. Genetic Algorithm(GA) has known as a method of solving NP problem in various applications. Since a major drawback of the GA is that it needs a long computation time, the hardware implementation of Genetic Algorithm is focused on in recent studies. Conventional hardware GA uses the fixed length of chromosome but the proposed Evolvable Hardware uses the variable length of chromosome by the efficient 16 bit Pipeline Unit. Experimental results show that the proposed evolvable hardware is applicable to the implementation of the clone for Moore State machine.

• Journal of the Korean Institute of Intelligent Systems
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• v.24 no.4
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• pp.412-417
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• 2014

This paper presents the development and control of an omni-directional holonomic mobile robot platform, which is equipped with three lateral orthogonal-wheel assemblies. Omni-directionality can be achieved with decoupled rotational and translational motions. Simulation studies on collision avoidance are conducted. A real robot is built and its hardware is implemented to control the robot. Control algorithm is embedded on DSP and FPGA chips. Hardware for motor control such as PWM, encoder counter, serial communication modules is implemented on an FPGA chip. Experimental studies of following joystick commands are performed to demonstrate the functionality and controllability of the robot.