• Journal of KIISE
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• v.44 no.1
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• pp.13-20
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• 2017

A message processor is server software that receives various message formats from clients, creates the corresponding threads to process them, and lastly delivers the results to the destination. Considering that each function of an SEDA-based message processor has its own characteristics such as CPU-bound or IO-bound, this paper proposes a thread-mapping strategy called "FC-TM" (function-characteristic aware thread mapping) that schedules the threads to the cores based on the function characteristics in multi-core environments. This paper assumes that message-processor functions are static in the sense that they are pre-defined when the message processor is built; therefore, we profile each function in advance and map each thread to a core using the information in order to maximize the throughput. The benchmarking results show that the throughput increased by up to a maximum of 72 % compared with the previous studies when the ratio of the IO-bound functions to the CPU-bound functions exceeds a certain percentage.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.168-171
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• 1999

A fault-tolerant system should have a high availability and high reliability to maintain a given system stable against sudden faults in the system. In this paper, we propose a new types of fault tolerant system based on a fault detection bus. The fault detection bus is designed and implemented to detect any errors by comparing event-output signals from two processor modules. It employs the hot standby sparing fault detection method〔1〕 to provide continuity of services even if a system fault occurs. The prototype fault tolerant system is currently being implemented on a management system with two processor modules.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.7
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• pp.1335-1345
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• 1994

In this paper, the performance analysis of Inter-Processor Communication Network(IPCN) in a large-capacity digital switching system, TDX-10, is presented. The simulation model of IPCN is developed using discrete event model of SLAM II. The simulation results of maximum buffer length and mean waiting times at each node, and utilization of D-bus are derived. Finally, the maximum call handling capacity of IPCN is obtained by taking link speed into consideration.

• Journal of the Korea Society for Simulation
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• v.12 no.1
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• pp.73-83
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• 2003

This paper presents armed vehicle BAttle Group Simulation model(called BAGSim) which is an object-oriented simulation system for representing battle group engagement consisting of tanks and helicopters. BAGSim is designed in the evolutionary software life cycle approach with the Unified Software Development Process, and implemented with C++ language. BAGSim consists of a preprocessor for engagement scenario definition and simulation data set up, a main processor for triggering engagement event and advancing simulation clock, and a post processor to record simulation histories. Application scenario covers several type of engagement among command tanks, fight tanks, scout helicopters, attack helicopters, anti-tank guided missiles, and decoys. Thus, BAGSim can be effectively used as an analytic tool to examine some operational concepts and tactics, further experimentally fine tune tank design options.

• Journal of Korea Multimedia Society
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• v.6 no.4
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• pp.638-649
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• 2003

In this monograph, we developed a Remote Courseware Management System so we can more easily cultivate a courseware with various multimedia applications through an easy interface with the internt. In the view of Developer of view, we could develop RCMS rapidly using the application of ASP.NET and have tried to adapt ourself to the future environment using it. ASP.NET provides much richer event programming model than ASP and event processor which are executed on Server. In the view of User, they can used the Internet service with equipment that they want at any place and any time. To control any kinds of courseware for Administrator and Users, we offered a variety of Multimedia applications and an easy interface and built a new style of web courseware.

• Proceedings of the Computational Structural Engineering Institute Conference
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• 1995.10a
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• pp.215-222
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• 1995

The objective of this paper is to develop a finite element structural analysis program using VB(Visual Basic) which has been recently getting popular as development tools of application program for Windows. VB provides several functions to develop an application program easily by supporting event-driven programming method and graphic object as control data type. This system is an integrated processor including preprocessor, solver and postprocessor. Automatic mesh generation is available at preprocess stage, and graphic presentation of deformation and stress is also represented at postprocess one.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.12
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• pp.704-715
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• 2004

Recently, a single or multi processor system uses the hierarchical memory structure to reduce the time gap between processor clock rate and memory access time. A cache memory system includes especially two or three levels of caches to reduce this time gap. Moreover, one of the most important things In the hierarchical memory system is the hit rate in level 1 cache, because level 1 cache interfaces directly with the processor. Therefore, the high hit rate in level 1 cache is critical for system performance. A victim cache, another high level cache, is also important to assist level 1 cache by reducing the conflict miss in high level cache. In this paper, we propose the advanced high level cache management scheme based on the processor reuse information. This technique is a kind of cache replacement policy which uses the frequency of processor's memory accesses and makes the higher frequency address of the cache location reside longer in cache than the lower one. With this scheme, we simulate our policy using Augmint, the event-driven simulator, and analyze the simulation results. The simulation results show that the modified processor reuse information scheme(LIVMR) outperforms the level 1 with the simple victim cache(LIV), 6.7% in maximum and 0.5% in average, and performance benefits become larger as the number of processors increases.

• Journal of Astronomy and Space Sciences
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• v.18 no.2
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• pp.163-173
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• 2001

In this paper, space radiation environment and single event effect(SEE) have been analyzed for the KOMPSAT-2 operational orbit. As spacecraft external and internal space environment, trapped proton, SEP(solar energetic particle) and GCR(galactic cosmic ray) high energy Protons and heavy ions spectrums are analyzed. Finally, SEU and SEL rate prediction has been performed for the Intel 80386 microprocessor CPU that is planned to be used in the KOMPSAT-2. As the estimation results, under nominal operational condition, it is predicted that trapped proton and high energetic proton induced SBU effect will not occur. But, it is predicted that heavy ion induced SEU can occur several times during KOMPSAT-2 3-year mission operation. KOMPSAT-2 has been implementing system level design to mitigate SEU occurrence using processor CPU error detection function of the on-board flight software.

• Annals of Clinical Neurophysiology
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• v.2 no.1
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• pp.8-12
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• 2000

Purpose : The rapid development and wide popularity of Digital EEG(DEEG) is due to its convenience, accuracy and applicability for quantitative analysis. These advantages of DEEG make one hesitate to use analog EEG(AEEG). To assess the advantage of DEEG system utilizing AEEG(DAEEG) over conventional AEEG and the clinical applicability, a DAEEG system was developed and applied to animal model Methods : Sprague-Dawley rat as status epilepticus model were used for collecting the EEG data. After four epidural electrodes were inserted and connected to 8-channel analog EEG(Nihon-Kohden, Japan), continous. EEG monitoring via computer screen was done from two rats simultaneously. EEG signals through analog amplifier and filters were digitized at digital signal processor and stored in Windows-based pentium personal computer. Digital data were sampled at a rate of 200 Hz and 12 bit of resolution. Acquisition software was able to carry out 'real-time view, sensitivity control and event marking' during continuous EEG monitoring. Digital data were stored on hard disk and hacked-up on CD-ROM for off-line review. Review system consisted of off-line review, saving and printing out interesting segment and annotation function. Results: This DAEEG system could utilize most major functions of DEEG sufficiently while making a use of an AEEG. It was easy to monitor continuously compared to Conventional AEEG and to control sensitivity during ictal period. Marking the event such as a clinical seizure or drug injection was less favorable than AEEG due to slowed processing speed of digital processor and central processing unit. Reviewing EEG data was convenient, but paging speed was slow. Storage and management of data was handy and economical. Conclusion : Relatively simple digital EEG system utilizing AEEG can be set-up at n laboratory level. It may be possible to make an application for clinical purposes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.1B
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• pp.71-79
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• 2011

This paper proposes a compiled-code simulator generation system based-on machine description language for efficient design space exploration in designing an embedded system optimized for a specific application. The proposed system generates a compiled-code simulator which maintains the functional accuracy of an event-driven simulator by determining instruction fetch and decoding processes statically. Generated simulator takes instruction-level and cycle-level simulation for estimating performances in embedded core. To show the efficiency of the constructed compiled-code simulator generator, architecture exploration had been performed for the JPEG encoder application. Starting with MIPS R3000 processor for one embedded core, the proposed system can produce the core showing optimized execution time for the application programming. In this process, a huge amount of simulation time has been used. Cycle-level compiled-code simulator has the functional accuracy and shows performance improvement by 21.7% in terms of simulation speed on the average when compared with an event-driven simulator.