• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.280-283
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Journal of Electrical Engineering and Technology
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• v.6 no.2
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• pp.233-238
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• 2011

In the present work, a new approach is proposed for via interconnects of semiconductor devices, where multi-wall carbon nanotubes (MWCNTs) are used instead of conventional metals. In order to implement a selective growth of carbon nanotubes (CNTs) for via interconnect, the buried catalyst method is selected which is the most compatible with semiconductor processes. The cobalt catalyst for CNT growth is pre-deposited before via hole patterning, and to achieve the via etch stop on the thin catalyst layer (ca. 3nm), a novel 2-step etch scheme is designed; the first step is a conventional oxide etch while the second step chemically etches the silicon nitride layer to lower the damage of the catalyst layer. The results show that the 2-step etch scheme is a feasible candidate for the realization of CNT interconnects in conventional semiconductor devices.

• Journal of Sensor Science and Technology
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• v.32 no.5
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• pp.328-333
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• 2023

This study experimentally verified the etch rate of the SiO₂ sacrificial layer etching process with a single etch hole using vapor-phase hydrogen fluoride (VHF) etching. To fabricate small-sized polysilicon etch holes, both circular and triangular pattern masks were employed. Etch holes were fabricated in the polysilicon thin film on the SiO₂ sacrificial layer, and VHF etching was performed to release the polysilicon thin film. The lateral etch rate was measured for varying etch hole sizes and sacrificial layer thicknesses. Based on the measured results, we obtained an approximate equation for the etch rate as a function of the etch hole size and sacrificial layer thickness. The etch rates obtained in this study can be utilized to minimize structural damage caused by incomplete or excessive etching in sacrificial layer processes. In addition, the results of this study provide insights for optimizing sacrificial layer etching and properly designing the size and spacing of the etch holes. In the future, further research will be conducted to explore the formation of structures using chemical vapor deposition (CVD) processes to simultaneously seal etch hole and prevent adhesion owing to polysilicon film vibration.

• Electrical & Electronic Materials
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• v.8 no.1
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• pp.90-94
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• 1995

Reactive Ion Etching(RIE) of Si$_{3}$N$_{4}$ in a CF$_{4}$/O$_{2}$ gas plasma exhibits such good anisotropic etching properties that it is widely employed in current VLSI technology. However, the RIE process can cause serious damage to the silicon surface under the Si$_{3}$N$_{4}$ layer. When an atmospheric pressure chemical vapor deposited(APCVD) SiO$_{2}$ layer is used as a etch-stop material for Si$_{3}$N$_{4}$, it seems inevitable to get a good etch selectivity of Si$_{3}$N$_{4}$ with respect to SiO$_{2}$. Therefore, we have undertaken thorough study of the dependence of the etch rate of Si$_{3}$N$_{4}$ plasmas on $O_{2}$ dilution, RF power, and chamber pressure. The etch selectivity of Si$_{3}$N$_{4}$ with respect to SiO$_{2}$ has been obtained its value of 2.13 at the RF power of 150 W and the pressure of 110 mTorr in CF$_{4}$ gas plasma diluted with 25% $O_{2}$ by flow rate.

• New & Renewable Energy
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• v.5 no.1
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• pp.26-31
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• 2009

The surface etching characteristics of single crystalline silicon wafer were investigated using potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH). The saw damage layer was removed after 10min by KOH 45wt% solution at $80^{\circ}C$. The wafer etched at high temperature ($90^{\circ}C$) and in low concentration (4wt%) of TMAH solution showed an increased etch rate of silicon wafer and wavy patterns on the surface. Especially, pyramidal textures were formed in 4wt% TMAH solution without alcohol additives.

• Korean Journal of Materials Research
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• v.3 no.5
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• pp.482-496
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• 1993

Radiation damage and contamination of silicons etched in the $CF_4+H_2$ and $CHF_3$ magnetron discharges have been characterized using Schottky diode characteristics, TEM, AES, and SIMS as a function of applied magnetic field strength. It turned out that, as the magnetic field strength increased, the radiation damage measured by cross sectional TEM and by leakage current of Schottky diodes decreased colse to that of wet dtched samples especially for $CF_4$ plasma etched samples, For $CF_4+H_2$and $CHF_3$ etched samples, hydrogen from the plasmas introduced extended defects to the silicon and this caused increased leakage current to the samples etched at low magnetic field strength conditions by hydrogen passivation. The thickness of polymer with the increasing magnetic field strength and showed the minimum polymer residue thickness near the 100Gauss where the silicon etch rate was maximum. Also, other contaminants such as target material were found to be minimum on the etched silicon surface near the highest etch rate condition.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.523-523
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• 2012

As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.171-174
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• 2002

The barium strontium titannate (BST) thin films were etched in $CF_{4}/Ar$ inductively coupled plasma (ICP). The high etch rate obtained at a $CF_{4}(20%)/Ar(80%)$ and the etch rate in pure argon was twice higher than that in pure $CF_{4}$. This indicated that BST etching is sputter dominant process. It is impossible to avoid plasma-induced damages by the energetic particles in the plasma and the nonvolatile etch products. The plasma damages were evaluated in terms of leakage current density, residues on the etched sample, and the changes of roughness. After the BST thin films exposed in the plasma, the leakage current density and roughness increases. In addition, there are appeared a nonvolatile etch byproductsand from the result of X-ray photoelectron spectroscopy (XPS). After annealing at ${600^{\circ}C}$ for 10 min in $O_{2}$ ambient, the increased leakage current density, roughness and nonvolatile etch byproducts reduced. From the this results, the plasma induced damage recovered by annealing process owing to the relaxation of lattice mismatches by Ar ions and the desorption of metal fluorides in high temperature.

• Journal of Sensor Science and Technology
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• v.24 no.1
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• pp.10-14
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• 2015

This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.198-198
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• 2013

Metal-Oxide-Semiconductor (MOS)에서 사용되는 다양한 channel materials로 high electron mobility을 가지는 III-V compound semiconductor가 대두되고 있다 [1,2]. 하지만 이러한 III-V compound semiconductor는 Si에 비해 안정적인 native oxide가 부족하기 때문에 Si, Ge, Al2O3과 BeO 등과 같은 다양한 물질들의 interface passivation layers (IPLs)에 대한 연구가 많이 되고 있다. 이러한 IPLs 물질은 0.5~1.0 nm의 매우 얇은 physical thickness를 가지고 있고 또한 chemical inert하기 때문에 플라즈마 식각에 대한 연구가 되고 있지만 IPLs 식각 후 기판인 III-V compound semiconductor에 physical damage과 substrate recess를 줄이기 위해서 높은 선택비가 필요하다. 이러한 식각의 대안으로 원자층 식각이 연구되고 있으며 이러한 원자층 식각은 반응성 있는 BCl3의 adsorption과 low energy의 Ar bombardment로 desorption으로 self-limited한 one monolayer 식각을 가능하게 한다. 그러므로 본 연구에서는, III-V compound semiconductor 위에 IPLs의 adsorption과 desorption의 cyclic process를 이용한 원자층식각으로 다양한 물질인 SiO2, Al2O3 (self-limited one monolayer etch rate=about 1 ${\AA}$/cycle), BeO (self-limited one monolayer etch rate=about 0.75 ${\AA}$/cycle)를 얻었으며 그 결과 precise한 etch depth control로 minimal substrate recess 식각을 할 수 있었다.