• The Transactions of the Korean Institute of Electrical Engineers
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• v.35 no.11
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• pp.487-494
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• 1986

This paper is concerned with the techniques of error check and reduction of state diagram using logic programming. Error check program aims to check not only syntax errors but also semantic errors. And reduction program optimizes the state diagram by finding the redundant equivalence states and removing those from the set of states. The input of both program is state diagram represented as state table form. The output of error check program is error comment. The output of reduction program is equivalence reduced state table. Both programs are implemented using prolog. Prolog has very powerful pattern matching, and its automatic back-tracking capabilities facilitate easy-to-write error check and reduction programs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1666-1668
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• 2004

By wireless transmission data, there is high possibility to get distortion and lose by noise and barrier on wireless. If the data check damaged and lost at receiver, can't make it clear and can't judge whether this data is right or not. Therefore, by wireless transmission data need the data error check algorithm in order to decrease the data's distortion and lose and to monitoring the transmission data as real time. This study consists of RF station for wireless transmission, Water Level Meter station for water level measurement and Error check algorithm for error check of transmission data. This study is also that investigation and search for error check algorithm in order to wireless digital data transmission in condition of the least data's damage and lose. Designed transmitter and receiver with one - chip micro process to protect to swell the volume of circuit. Had designed RF transmitter - receiver station simply by means of ATMEL one - chip micro process in the systems. Used 10mW of the best RF power and 448MHz-449MHz on frequency band which can get permission to use by Frequency Law made by Korean government

• The Transactions of The Korean Institute of Electrical Engineers
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• v.57 no.1
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• pp.128-136
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• 2008

In this paper, we propose a new cache structure for effective error correction of soft error. We added check bit and SEEB(soft error evaluation block) to evaluate the status of cache line. The SEEB stores result of parity check into the two-bit shit register and set the check bit to '1' when parity check fails twice in the same cache line. In this case the line where parity check fails twice is treated as a vulnerable to soft error. When the data is filled into the cache, the new replacement algorithm is suggested that it can only use the valid block determined by SEEB. This structure prohibits the vulnerable line from being used and contributes to efficient use of cache by the reuse of line where parity check fails only once can be reused. We tried to minimize the side effect of the proposed cache and the experimental results, using SPEC2000 benchmark, showed 3% degradation in hit rate, 15% timing overhead because of parity logic and 2.7% area overhead. But it can be considered as trivial for SEEB because almost tolerant design inevitably adopt this parity method even if there are some overhead. And if only parity logic is used then it can have $5%{\sim}10%$ advantage than ECC logic. By using this proposed cache, the system will be protected from the threat of soft error in cache and the hit rate can be maintained to the level without soft error in the cache.

• Journal of IKEEE
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• v.23 no.1
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• pp.22-28
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• 2019

This paper presents the monitoring method of machining error and quality check to improve the productivity of boring manufacturing process. Machining error usually appears as the offset of spatial location of actual cutting path compared to ideal cutting path. In order to monitor an error of workpiece, multiple factors affecting quality of boring, such as distortion of workpiece, clamping error, radial rotation error of the spindle and motion error of machine tools, were took into account. To verify the productive quality, we propose the quality check system. The system based on IT convergence analyzes the process error rate and saves the analyzed data in memory. Also, these play important roles in detecting an inferior production goods and can decrease the production cost and loss of bearing.

• ETRI Journal
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• v.37 no.1
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• pp.54-60
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• 2015

The use of serial concatenated codes is an effective technique for alleviating the error floor phenomenon of low-density parity-check (LDPC) codes. An enhanced sum-product algorithm (SPA) for LDPC codes, which is suitable for serial concatenated codes, is proposed in this paper. The proposed algorithm minimizes the number of errors by using the failed check nodes (FCNs) in LDPC decoding. Hence, the error-correcting capability of the serial concatenated code can be improved. The number of FCNs is simply obtained by the syndrome test, which is performed during the SPA. Hence, the decoding procedure of the proposed algorithm is similar to that of the conventional algorithm. The error performance of the proposed algorithm is analyzed and compared with that of the conventional algorithm. As a result, a gain of 1.4 dB can be obtained by the proposed algorithm at a bit error rate of $10^{-8}$. In addition, the error performance of the proposed algorithm with just 30 iterations is shown to be superior to that of the conventional algorithm with 100 iterations.

• Journal of the Korean Society of Safety
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• v.13 no.4
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• pp.279-285
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• 1998

This study investigated human error characteristics of the 42 fatal industrial accidents reported by staff members of Korea Industrial Safety Corporation. Various types of human error were judged to be primary contributing factors in about 74 percent of the cases. Most of human error made by involved industrial operators resulted from two types of mistakes: (1) mistake in judgement of work situation, and (2) omission in daily check. It was concluded that preparation/observance for work procedure manuals, danger predication training and enforcement/Education of daily check routine would be effective preventive tools for these types of human error attributable to fatal industrial accidents.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.993-997
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• 2004

A data error inspection algorithm for wireless digital data communication was developed. Original data converted By wireless digital data error inspection algorithm. Wireless digital data is high possibility to get distortion and lose by noise and barrier on wireless. If the data check damaged and lost at receiver, can't make it clear and can't judge whether this data is right or not. Therefore, by wireless transmission data need the data error inspection algorithm in order to decrease the data distortion and lose and to monitoring the transmission data as real time. This study consists of RF station for wireless transmission, Water Level Meter station for water level measurement and Error inspection algorithm for error check of transmission data. This study is also that investigation and search for error inspection algorithm in order to wireless digital data transmission in condition of the least data's damage and lose. Designed transmitter and receiver with one - chip micro process to protect to swell the volume of circuit. Had designed RF transmitter - receiver station simply by means of ATMEL one - chip micro processing the systems. Used 10mW of the best RF power and 448MHz-449MHz on frequency band which is open to public touse free within the limited power.

• The Journal of Korean Society for Radiation Therapy
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• v.13 no.1
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• pp.47-50
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• 2001

Purpose : 체내에서 optimal한 dose distribution을 얻기 위해 도입된 IMRT를 시행할 때 사용하는 MLC는 기계특성상 장기적인 check와 교정을 요한다. 또한 MLC는 static하지 않고 dynamic하기 때문에 leaf position의 실제 위치가 매우 중요하다. MLC QA를 위해 QA 소요시간 및 노력이 많이 MLC position check 요구되는 불편이 있어, 삼성서울 병원에서 필름을 이용한 MLC position check device를 제작하여 간편하게 사용하고 그 우수성에 대해 결과를 보고하고자 한다. Materials and Method : MLC position을 check하기위해 사각형 의 device(acryl:$40{\times}40{\times}5cm$)를 제작하였다. position check device의 정확도를 위해 표면에 real scale 표시용으로 Pb marker를 2cm 간격으로 부착하였다. MLC QA film은 마주보는 (opposite) MLC leaf의 간격이 4mm로 set up한 상태에서 double exposure하여 marker를 이용하여 오차를 분석하였다. MLC position check device의 효율성을 평가하기위해 6MV photon으로 10번 반복 실험을 실시하여 MLC leaf의 평균오차를 조사하고 조사에 걸린 시간을 비교하여 유용성을 평가하였다. Results : 실험결과 MLC leaf의 평균오차를 조사하고 조사에 걸린 시간을 비교하여 유용성을 평가하였다. 범위는 1.45mm였고, 최소 오차는 0.34mm로 나타났다. 1회 조사에 걸린 시간은 평균적으로 약 30분 정도 소요되었다. MLC position check device의 효율성을 평가한 결과오차의 반복성은 관찰되지 않았다. Conclusion : MLC leaf position의 정기적인 check와 교정을 위해 본원에서는 주1회 정기 position error를 check하고 있으며, 평균 월1회 교정을 한다. 본 실험을 통해 MLC position check device를 사용하여 leaf 오차가 2mm이하의 만족할 만한 결과를 얻었다. 또한 MLC position check device를 사용하면 짧은 시간에 모든 leaf의 position error를 쉽게 측정할 수 있고 한 장의 필름으로 모든 결과를 평가할 수 있어 경제성 및 업무의 효율성도 높일 수 있었다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.15 no.2
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• pp.485-499
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• 2021

Although non-binary low-density parity-check (NB-LDPC) codes have better error-correction capability than that of binary LDPC codes, their decoding complexity is significantly higher. Therefore, it is crucial to reduce the decoding complexity of NB-LDPC while maintaining their error-correction capability to adopt them for various applications. The extended min-sum (EMS) algorithm is widely used for decoding NB-LDPC codes, and it reduces the complexity of check node (CN) operations via message truncation. Herein, we propose a low-cost CN processing method to reduce the complexity of CN operations, which take most of the decoding time. Unlike existing studies on low complexity CN operations, the proposed method employs quick selection algorithm, thereby reducing the hardware complexity and CN operation time. The experimental results show that the proposed selection-based CN operation is more than three times faster and achieves better error-correction performance than the conventional EMS algorithm.