• ETRI Journal
• /
• 제29권6호
• /
• pp.785-793
• /
• 2007

In this paper, we present an integrated rail-to-rail fully differential operational transconductance amplifier (OTA) working at low-supply voltages (1.5 V) with reduced power consumption and showing high DC gain. An embedded adaptive biasing circuit makes it possible to obtain low stand-by power dissipation (lower than 0.17 mW in the rail-to-rail version), while the high DC gain (over 78 dB) is ensured by positive feedback. The circuit, fabricated in a standard CMOS integrated technology (AMS 0.35 ${\mu}m$), presents a 37 V/${\mu}s$ slew-rate for a capacitive load of 15 pF. Experimental results and high values of two quality factors, or figures of merit, show the validity of the proposed OTA, when compared with other OTA configurations.

• 전기학회논문지
• /
• 제65권6호
• /
• pp.955-961
• /
• 2016

Fault location estimation is an important element for rapid recovery of power system when fault occur in transmission line. In order to calculate line impedance, most of fault location algorithm uses by measuring relaying waveform using DFT. So if there is a calculation error due to the influence of phasor by DC offset component, due to large vibration by line impedance computation, abnormal and non-operation of fault locator can be issue. It is very important to implement the robust fault location algorithm that is not affected by DC offset component. This paper describes an enhanced fault location algorithm based on the DC offset elimination filter to minimize the effects of DC offset on a long transmission line. The proposed DC offset elimination filter has not need any erstwhile information. The phase angle delay of the proposed DC offset filter did not occurred and the gain error was not found. The enhanced fault location algorithm uses DFT filter as well as the proposed DC offset filter. The behavior of the proposed fault location algorithm using off-line simulation has been verified by data about several fault conditions generated by the ATP simulation program.

• 전기학회논문지P
• /
• 제60권3호
• /
• pp.126-132
• /
• 2011

A conventional LDO(Low Dropout Regulator) uses one OPAMP and one signal path. This means that OPAMP's DC Gain and Bandwidth can't optimize simultaneously within usable power. This also appears that regulation property and settling time of LDO can't improve at the same time. Based on this idea, a proposed LDO uses two OPAMP and has two signal path. To improve regulation property, OPAMP where is used in the path which qualities DC gain on a large scale, bandwidth designed narrowly. To improve settling time, OPAMP where is used in the path which qualities DC gain small, bandwidth designed widely. A designed LDO used 0.5um 1P2M process and provided 200mA of output current. A line regulation and load regulation is 12.6mV/V, 0.25mV/mA, respectively. And measured settling time is 1.5us in 5V supply voltage.

• 전기학회논문지P
• /
• 제64권2호
• /
• pp.67-73
• /
• 2015

Distance relay is widely used for the protection of long transmission line. Most of distance relay used to calculate line impedance by measuring voltage and current using DFT. So if there is a computation error due to the influence of phasor by DC offset component, due to excessive vibration by measuring line impedance, overreach or underreach can be occurs, and then abnormal and non-operation of distance relay can be issue. It is very important to implement the robust distance relaying that is not affected by DC offset component. This paper describes an enhanced distance relaying based on the DC offset elimination filter to minimize the effects of DC offset on a long transmission line. The proposed DC offset elimination filter has not need any prior information. The phase angle delay of the proposed DC offset filter did not occurred and the gain error was not found. The enhanced distance relay uses fault current as well as residual current. The behavior of the proposed distance relaying using off-line simulation has been verified using data about several fault conditions generated by the ATP simulation software.

• 전력전자학회논문지
• /
• 제18권4호
• /
• pp.305-311
• /
• 2013

This paper proposes a performance improvement of existing single-phase current-fed qZ-Source inverter. Voltage gain of the traditional voltage-fed full-bridge inverter and single-phase current-fed qZ-source inverter is only equal to or smaller than input voltage. The proposed inverter can obtain twice higher voltage gain than the single-phase current-fed qZ-Source inverter by adding an extra switch and a capacitor in the circuit. In addition, the proposed inverter shares the common ground between dc input and ac output voltage. Therefore, the proposed inverter can eliminate the possible ground leakage current problem when it is used for grid-tied photovoltaic inverter system. A 120 W prototype inverter is built and tested to verify performances of the proposed inverter.

• Journal of Power Electronics
• /
• 제17권6호
• /
• pp.1422-1432
• /
• 2017

This paper presents a buck-boost converter-based bipolar pulse generator, which is able to generate bipolar exponential pulses across a resistive load. The concept of the proposed approach depends on operating the involved buck-boost converters in discontinuous current conduction mode with high-voltage gain and enhanced efficiency. A full design of the pulse generator and its passive components is presented to ensure generating the pulses with the desired specifications (rise time, pulse width, and pulse magnitude) for a given load resistance and input dc voltage. In case of moderate pulsed output voltages (i.e. few of kV), one module of the presented bipolar generator can be employed. While in case of high-voltage pulsed output, multi-module version can be employed, where each module is fed from an isolated dc source and their outputs are connected in series. Simulation models for the proposed approach are built to elucidate their performance in case of one-module as well as multi-module based generator. Finally, a scaled-down prototype for one-module of buck-boost converter-based bipolar pulse generator is implemented to validate the proposed concept.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(2)
• /
• pp.663-666
• /
• 2003

This paper presents a speed controller method based on the disturbance torque observer of high performance brushless DC (BLDC) motor drives. In case of the speed control of robot arms and tracking applications with lower stiffness, we cannot design the speed controller gain to be very large from tile viewpoint of the system stability. Thus, the feedforward compensator using disturbance torque observer was proposed. This method can improve the speed characteristic without increasing the speed controller gain. The enhanced speed control performance can be achieved and the speed response against the disturbance torque can be Improved for high-performance BLDC motor drive systems in which the bandwidth of tile speed controller cannot be made large enough. Consequently, speed control for high-performance BLDC motor drives become improved. The simulation results for BLDC motor drive systems confirm the validity of the proposed method.

• 한국전자파학회:학술대회논문집
• /
• 한국전자파학회 2003년도 종합학술발표회 논문집 Vol.13 No.1
• /
• pp.389-393
• /
• 2003

This paper describes the design of enhanced TSSI RF Power Detector which has wide dynamic range using switch and Log amp. This Power Detector consists of low and high gain loops, and they adaptively switched by output DC voltage which is proportioned to input power level. Because Power Detector needs to separate the channel, so architecture is heterodyne system having 70MHz intermediate frequency. This proposed RF Power Detector is settle to the satisfaction of Closed loop power control system for W-CDMA optic repeater, and the obtained dynamic range cover the higher than 50dB.

• 방송공학회논문지
• /
• 제21권3호
• /
• pp.319-329
• /
• 2016

인터넷 비디오 코딩(Internet Video Coding: IVC)은 MPEG에서 개발 중인 로열티 무료 비디오 코덱이다. IVC 코덱의 부호화 효율은 지속적으로 향상되어왔으며, CD(Committee Draft) 버전의 IVC는 객관적 화질 및 주관적 화질이 H.264/AVC HP(High Profile)와 견줄 만한 수준의 성능을 낸다고 보고 되었다. 본 논문에서는 IVC 코덱 구조의 개요 및 주요 부호화 알고리즘과 함께 MPEG에서의 IVC 개발 과정 중에 부호화 효율을 향상시키기 위하여 제안된 부호화 툴을 제시한다. 부호화 툴은 비 참조 P 프레임 부호화, DC 모드 화면내 예측, 라그랑지안 승수(Lagrange Multiplier) 선택기법, 색차신호의 화면내 예측모드 확장 기법 등 표준 및 비표준 부호화 기법을 포함한다. 각 부호화 툴에 대한 알고리즘과 부호화 효율 이득을 실험을 통하여 제시하였다. 실험결과 각 부호화 툴은 저지연 부호화 모드에서 각각 8.8%, 0.4%, 0.4%, 0.0%의 비트율 절감의 부호화 이득을 얻었다.

• 전기전자학회논문지
• /
• 제19권4호
• /
• pp.506-513
• /
• 2015

본 논문에서는 외부 커패시터가 없는 low-dropout (LDO) 레귤레이터를 설계하였으며, 대기 전류는 $4.5{\mu}A$ 이다. 제안하는 LDO 레귤레이터는 정밀한 로드 레귤레이션과 빠른 응답 속도를 만족하기 위해 두 개의 증폭기를 사용 하였고, 높은 이득을 갖는 증폭기와 빠른 속도 및 높은 슬루율을 가지는 증폭기로 구성 되어 있다. 이와 함께 패스 트랜지스터의 게이트에 존재하는 큰 기생 커패시터에 전류를 빠르게 충 방전시키기 위해, 전류 부스팅 회로를 추가하였다. 이를 통해 부하 전류 변화 시 응답 시간을 향상 시키게 된다. 설계된 회로는 $0.11-{\mu}m$ CMOS 공정으로 제작되었다. 최대 200mA 의 부하 전류를 구동할 수 있으며, 출력 전압 변동은 260mV, 회복 시간은 $0.8{\mu}s$ 을 측정하였다.