• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.476-478
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• 1997

A new speed detection method using low resolution incremental encoders, especially excellent in the low speed region and in the transient state, is proposed. The half period error of an incremental encoder is greater than the period error. So it's not recommended to quadruple the number of pulses per revolution, because it increase the ripple of speed. To overcome this restriction a speed detection, method has been proposed. But it requires so many latch circuits. Therefore we propose a new speed detection method that has different concept and has fewer latch circuits.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.30 no.9 s.252
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• pp.1094-1101
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• 2006

Recently, a ultra-precision stage is widely used in the fields of the nano-technology, specially in AFMs(Atomic Force Microscope) and STMs(Scanning Tunneling Microscope). In this paper, the ultra-precision stage which consists of flexure hinges, piezoelectric actuator and ultra-precision linear encoder, is designed and developed. The system transfer function of the ultra-precision stage system was derived from the step responses of the system using system identification tool. A $H_{\infty}$ controller was designed using loop shaping method to have robustness for the system uncertainty and external disturbances. For the designed controller, simulations were performed and it was applied to the ultra-precision stage system. From the experimental results it was found that this stage could be controlled with less than 5nm resolution irrespective of hysteresis and creep.

• The Transactions of the Korean Institute of Power Electronics
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• v.1 no.1
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• pp.12-19
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• 1996

The purpose of this paper is the improvement of the speed control characteristics of induction machines suited the low resolution incremental-type encoder in a low speed region. In order to improve the control characteristics in a low speed range, we propose that the instantaneous speed control method by the instantaneous speed detection which is implemented by the disturbance torque observer. Also, in case of the speed control by the instantaneous speed detection, the simple estimation method of the mechanical inertia moment is proposed. We will the carry out the mathematical verification of the proposed theory by the theoretic advisement connected with the convergence relationship of the estimated inertia moment to the real mechanical inertia moment. Computer simulations and experiments by the IGBT inverter adopting DSP is performed to verify the proposed method.

• Journal of Electrical Engineering and Technology
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• v.11 no.4
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• pp.931-938
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• 2016

Application of vector control scheme for consumer products is enlarging to improve control performance. For the field-oriented control, accurate position detection is essential and generally requires expensive sensors. On the other hand, cost-reduction is important in home appliances, so that binary-type Hall-effect sensors are commonly used rather than using an expensive sensor such as an encoder. The control performance is directly influenced by the accuracy of the position information, and there exist non-uniformities related to Hall sensors in electrical and mechanical aspects, which result in distorted position information. Therefore, to get high-precision position information from low-resolution Hall sensors, this paper proposes a new position estimator consisting of a Kalman filter and feedforward compensation scheme, which generates a linearly changing position signal. The efficacy of the proposed scheme is verified by simulation and experimental results carried out with a 48-pole permanent magnet motor.

• Proceedings of the KIEE Conference
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• 2005.07b
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• pp.1129-1131
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• 2005

본 논문은 저가형 고정도 아날로그 디지털 혼합형 엔코더에서 센서 취부 오차에 의해 발생하는 정지 2축 좌표상의 두 아날로그신호의 크기, 위상오차 문제 보상에 관한 연구이다. 기존의 혼합형 엔코더에서 문제시되고 있는 두 아날로그 위치정보 신호의 크기문제는 상대 크기에 대하여 정규화 함으로써 해결하였으며, 센서 취부시 발생하는 위치오차문제는 정지 2축 좌표축을 센서의 위치 오차분을 보상할 수 있도록 회전함으로써 보상할 수 있었다. 또한 제안된 새로운 방식의 위치 검출기법을 DSP의 QEP기능과 A/D변환기를 사용한 실험을 통하여 그 타당성을 검증하였다.

• Journal of Broadcast Engineering
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• v.27 no.7
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• pp.1011-1020
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• 2022

Recent high-performance panoptic segmentation models are based on transformer architectures. However, transformer-based panoptic segmentation methods are basically slower than convolution-based methods, since the attention mechanism in the transformer requires quadratic complexity w.r.t. image resolution. Also, sine and cosine computation for positional embedding in the transformer also yields a bottleneck for computation time. To address these problems, we adopt three modules to speed up the inference runtime of the transformer-based panoptic segmentation. First, we perform channel-level reduction using depth-wise separable convolution for inputs of the transformer decoder. Second, we replace sine and cosine-based positional encoding with convolution operations, called conv-embedding. We also apply a separable self-attention to the transformer encoder to lower quadratic complexity to linear one for numbers of image pixels. As result, the proposed model achieves 44% faster frame per second than baseline on ADE20K panoptic validation dataset, when we use all three modules.

• Journal of the Korean Society for Precision Engineering
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• v.12 no.2
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• pp.37-47
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• 1995

In recent years, it has been variously developed for testing the accuracy of circular motion of NC machine tools, for example Telescoping Ball Bar Method by Bryan, Circular test Method by Knapp and $r^{-{\theta} }$ Method by Tsutsumi etc., but these methods are all 2-dimentional measuring methods on plane. These simple methods of circular motion accuracy test of NC machine tools have been studied by many reserchers as above, but it is not yet settled in the code of measuring methods of motion errors of NC machine tools, because of errors of measuring units and sensors, and also especially the difficulties of centering of measuring units and the spindle of machining center. In this paper, in use of 2 rotary encoders and 1 magnetic type linear scale with resolution of 0.5 .mu. m, it has become possible for measuring of 3 dimentional space motion accuracy.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.7
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• pp.107-118
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• 2015

Although most current video coding standards set a fixed motion vector resolution like quarter-pel accuracy, a scheme supporting multiple motion vector resolutions can improve the coding efficiency of video since it can allow to use just required motion vector accuracy depending on the video content and at the same time to generate more accurate motion predictor. However, the selected motion vector resolution for each motion vector is a signaling overhead. This paper proposes a contradiction testing-based signaling scheme of the motion vector resolution. The proposed method selects a best resolution for each motion vector among multiple candidates in such a way to produce the minimum amount of coded bits for the motion vector. The signaling overhead is reduced by contradiction testing that operates under a predefined criterion at both encoder and decoder with a purpose of pruning irrelevant candidate motion vector resolutions from signaling responsibility. Experimental results verified that the proposed scheme is effective in reducing coded motion information by achieving its $Bj{\o}ntegaard$ delta bit rate (BDBR) gain of about 4.01% on average (and up to 15.17%) compared to the conventional scheme with a fixed motion vector resolution.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.11
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• pp.13-20
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• 2008

In this paper, an 1.8V 12-bit 10MSPS CMOS A/D converter (ADC) is described. The architecture of the proposed ADC is based on a folding and interpolation using an even folding technique. For the purpose of improving SNR, cascaded-folding cascaded-interpolation technique, distributed track and hold are adapted. Further, a digital encoder algorithm is proposed for efficient digital process. The chip has been fabricated with $0.18{\mu}m$ 1-poly 4-metal n-well CMOS technology. The effective chip area is $2000{\mu}m{\times}1100{\mu}m$ and it consumes about 250mW at 1.8V power supply. The measured SNDR is about 46dB at 10MHz sampling frequency.

• Journal of Broadcast Engineering
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• v.11 no.3 s.32
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• pp.320-325
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• 2006

An image is partitioned into non-overlapping $8{\times}8$ blocks fer JPEG compression. A scan order converter is placed before the JPEG encoder to provide $8{\times}8$ blocks from the pixels in raster scan order. In general, its architecture requires two line memories for storing eight lines separately to allow the concurrent memory access by both the camera and JPEG processors. Although such architecture is simple to be implemented, it can be inefficient due to too excessive memory requirement as the image resolution increases. However, no deterministic addressing equation has been developed for scan conversion. In this paper, an effective memory addressing algorithm is proposed that can be devised only by adders and subtracters to implement a scan converter based on the single line memory.