• 제목/요약/키워드: elimination method

검색결과 979건 처리시간 0.024초

구조물의 손상탐지를 위한 역섭동법과 센서위치의 선정 (Inverse Perturbation Method and Sensor Location for Structural Damage Detection)

  • 박윤철;최영재;조진연;김기욱
    • 한국항공우주학회지
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    • 제31권3호
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    • pp.31-38
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    • 2003
  • 본 연구는 최적설계에 사용되는 역섭동법을 구조물의 손상탐지에 적용하였다. 이 방법은 손상의 위치를 정확하게 탐지하기 위하여 미지수보다 많은 수의 구속조건이 필요하므로, 최적설계와는 달리 비선형 회소자승법을 수치기법에 사용한다. 한편 손상탐지의 경우, 모든 자유도의 응답이 측정가능한 것은 아니며 제한된 수의 센서에서 부분적인 진동모드만 측정할 수 있다. 이처럼 부분적인 정보를 사용하여, 손상진단을 성공적으로 수행하기 위해서는 사용될 센서의 수와 위치를 결정하는 연구가 매우 중요한다. 본 논문에서는 센서의 개수가 결정되었을 때, 손상탐지에 적합한 센서 위치의 선정방법에 관하여 연구하였다. 이러한 연구의 결과로 순차적 소거법이 역섭동법을 이용한 손상탐지에 가장 적합한 센서위치의 선정방법임을 수치 예에서 확인하였다.

Real time Implementation of SHE PWM in Single Phase Matrix Converter using Linearization Method

  • Karuvelam, P. Subha;Rajaram, M.
    • Journal of Electrical Engineering and Technology
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    • 제10권4호
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    • pp.1682-1691
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    • 2015
  • In this paper, a real time implementation of selective harmonic elimination pulse width modulation (SHEPWM) using Real Coded Genetic Algorithm (RGA), Particle Swarm Optimization technique (PSO) and a new technique known as Linearization Method (LM) for Single Phase Matrix Converter (SPMC) is designed and discussed. In the proposed technique, the switching frequency is fixed and the optimum switching angles are obtained using simple mathematical calculations. A MATLAB simulation was carried out, and FFT analysis of the simulated output voltage waveform confirms the effectiveness of the proposed method. An experimental setup was also developed, and the switching angles and firing pulses are generated using Field Programmable Gate Array (FPGA) processor. The proposed method proves that it is much applicable in the industrial applications by virtue of its suitability in real time applications.

정밀점 기구합성시 지정위치의 변경을 이용한 허근의 실수화 방법 (Derivation of Real Values from Imaginary Roots by Altering Prescribed Positions in the Precision Point Synthesis of Mechanisms)

  • 이태영;심재경;이재길
    • 한국정밀공학회지
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    • 제17권7호
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    • pp.196-202
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    • 2000
  • In the precision point synthesis of mechanisms, it is usually required to solve a system of polynomial equations. With the aid of efficient algorithms such as elimination, it is possible to obtain all the solutions of the equations in the complex domain. But among these solutions only real values can be used fur real mechanisms, while imaginary ones are liable to be discarded. In this article, a method is presented, which leads the imaginary solutions to real domain permitting slight alteration of prescribed positions and eventually increases the number of feasible mechanisms satisfying the desired motion approximately. Two synthesis problems of planar 4-bar path generation and spatial 7-bar motion generation are given to verify the proposed method.

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An Improved Non-CSD 2-Bit Recursive Common Subexpression Elimination Method to Implement FIR Filter

  • Kamal, Hassan;Lee, Joo-Hyun;Koo, Bon-Tae
    • ETRI Journal
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    • 제33권5호
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    • pp.695-703
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    • 2011
  • The number of adders and critical paths in a multiplier block of a multiple constant multiplication based implementation of a finite impulse response (FIR) filter can be minimized through common subexpression elimination (CSE) techniques. A two-bit common subexpression (CS) can be located recursively in a noncanonic sign digit (CSD) representation of the filter coefficients. An efficient algorithm is presented in this paper to improve the elimination of a CS from the multiplier block of an FIR filter so that it can be realized with fewer adders and low logical depth as compared to the existing CSE methods in the literature. Vinod and others claimed the highest reduction in the number of logical operators (LOs) without increasing the logic depth (LD) requirement. Using the design examples given by Vinod and others, we compare the average reduction in LOs and LDs achieved by our algorithm. Our algorithm shows average LO improvements of 30.8%, 5.5%, and 22.5% with a comparative LD requirement over that of Vinod and others for three design examples. Improvement increases as the filter order increases, and for the highest filter order and lowest coefficient width, the LO improvements are 70.3%, 75.3%, and 72.2% for the three design examples.

A comparison of the elimination rate of artificial dental plaque between reciprocating- and rotating-interdental toothbrushes

  • Lim, Kun-Ok
    • 한국치위생학회지
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    • 제21권1호
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    • pp.17-25
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    • 2021
  • Objectives: Interdental toothbrushes are made and sold in various design types and brush thicknesses. However, there is little research on which type of interdental toothbrush currently manufactured and sold on the market is the most effective in eliminating interdental plaque. Therefore, this study aims at comparing the elimination rate of artificial dental plaque between reciprocating- and rotating-types of interdental toothbrush based on the frequency of application and thickness of brush. Methods: This study focused on the effective management of dental plaque using interdental toothbrush, a recommended item for personal dental hygiene. The method was as follows: artificial dental plaque coloring was applied to the distal surface of artificial tooth #46 and the mesial surface of #47. The area was subject to reciprocal movement three and six times to eliminate artificial plaque. Results: The results showed that using a 0.7mm rotating interdental toothbrush, on the proximal surface of each molar, the elimination rates were: on the distal surface of #46, upon three applications 40.24%, upon six applications 30.41%; on the mesial surface of #47, upon three applications 44.52%, upon six applications 29.72%. Conclusions: These results showed that for rotating-type interdental toothbrushes, a high dental plaque elimination rate was observed even though many reciprocal movements were not performed.

고스트 신호 제거기용 애널러그 위상변위기 설계 (Design of the analog phase shifter for the ghost signal elimination)

  • 주성호;김동현;이상설
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 1999년도 추계종합학술대회 논문집
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    • pp.825-828
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    • 1999
  • In this paper, we design the analog phase shifter for the elimination of the ghost signal. Compensation of the delay between the reference signal and the relatively delayed signal is possible. This phase shifter uses the vector summing method. We use for the attenuator in our system FETs. The phase shifter is operated at the 200MHz and composed by lumped elements. The proposed analog phase shifter is simulated by the HP ADS software.

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Breakthrough of Single-Quantum Signal in Double-Quantum Filtering and its Elimination

  • 정관진;;;조장희
    • 대한의용생체공학회:학술대회논문집
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    • 대한의용생체공학회 1993년도 춘계학술대회
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    • pp.86-89
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    • 1993
  • Breakthrough of single-quantum coherence is shown to occur even after application of a double-quantum filter with Bax's four-step phase-cycling scheme. The reason for this breakthrough is investigated and a method for its elimination is theoretically developed and experimentally demonstrated.

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주자유도 선정을 위한 2단계 축소기법의 제안과 축소시스템 구성에 관한 연구 (Two-Level Scheme for Selection of Degrees of freedom by Energy Estimation Combined with Sequential Elimination)

  • 김현기;조맹효
    • 한국전산구조공학회:학술대회논문집
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    • 한국전산구조공학회 2004년도 봄 학술발표회 논문집
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    • pp.87-94
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    • 2004
  • A number of approximate techniques have been developed to calculate the eigenvalues in a reduced manner. These schemes approximate the lower eigenvalues that represent the global behavior of the structures. In general, sequential elimination has been widely used with reliability. But it takes excessively large amount of time to construct a reduced system. The present study proposes two-level condensation scheme(TLCS). In the first step, the candidate elements are selected by element-level energy estimation. In the second step, master degrees of freedom are selected by sequential elimination from the candidate degrees of freedom linked to the selected elements in the first step. Numerical examples demonstrate that the proposed method saves computational cost effectively and provides a reduced system which predicts the accurate eigenvalues of global system.

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Reconfigurable Selective Harmonic Elimination Technique for Wide Range Operations in Asymmetric Cascaded Multilevel Inverter

  • Kavitha, R;Rani, Thottungal
    • Journal of Power Electronics
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    • 제18권4호
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    • pp.1037-1050
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    • 2018
  • This paper presents a novel reconfigurable selective harmonic elimination technique to control harmonics over a wide range of Modulation Indexes (MI) in Multi-Level Inverter (MLI). In the proposed method, the region of the MI is divided into various sectors and expressions are formulated with different switching patterns for each of the sectors. A memetic BBO-MAS (Biogeography Based Optimization - Mesh Adaptive direct Search) optimization algorithm is proposed for solving the Selective Harmonic Elimination - Pulse Width Modulation (SHE-PWM) technique. An experimental prototype is developed using a Field Programmable Gate Array (FPGA) and their FFT spectrums are analyzed over a wide range of MI using a fluke power logger. Simulation and experimental results have validated the performance of the proposed optimization algorithms and the reconfigurable SHE-PWM technique. Further, the sensitivity of the harmonics has been analyzed considering non-integer variations in the magnitude of the input DC sources.

유동대전된 절연유의 제전방식중 필터에 의한 영향 (The Effect of Filter in the Static Charge Elimination Methodes for Streaming-Electrification Insulating Oil.)

  • 정광현;김용운;신재화;김보열;이덕출
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1995년도 추계학술대회 논문집
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    • pp.361-364
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    • 1995
  • The static charges are generated by streaming electrification phenomena when insulating oil flowing by force for the purpose of cooling at the internal of Ultra-high power transformer. In this thesis, their elimination method was studied. The falter represents a greet much electrification characteristics because falter has large interfaces with liquid. In this paper, the streaming-electrification phenomena of insulating oil by metal filter were measured by mesh number, oil flow rate, oil temperature and a kind of mesh and The effect of charge elimination by metal filter generated minus ion was measured.

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