• Journal of Information Display
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• v.5 no.1
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• pp.41-46
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• 2004

In this paper, a new stereo 3D moving-target tracking system using the MSE (mean square error) and BPEJTC (binary phase extraction joint transform correlator) algorithms is proposed. A moving target is extracted from the sequential input stereo image by applying a region-based MSE algorithm following which, the location coordinates of a moving target in each frame are obtained through correlation between the extracted target image and the input stereo image by using the BPEJTC algorithm. Through several experiments performed with 20 frames of the stereo image pair with $640{\times}480$ pixels, we confirmed that the proposed system is capable of tracking a moving target at a relatively low error ratio of 1.29 % on average at real time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.20 no.2
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• pp.173-177
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• 2007

Electro-wetting display (EWD) that displays information by controling movement of fluid is one of the strong candidates for electronic paper display (EPD). In EWD cell. the movement of oil which locates between hydrophobic insulation layer and deionized water is rather random, which makes it difficult to realize gray scale, fast response time, and good color characteristics. In this paper, we investigated how to control the oil movement in specific one direction by surface treatment and pattered electrodes. From these experiments, we could control oil movement in a desired direction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.85-86
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• 2008

We have developed charged particle type display using opposite-charged two particles. We fabricated the charged particle type display to be controlled the addressing layers by putting voltage. To get the effect of number of layers, we measured driving voltage, reflectivity, viewing angle, and color characteristics, for 1~2 layer. Reflectivity was different according to the number of layers and wavelength of yellow particles is alike to that.

• Electrical & Electronic Materials
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• v.12 no.7
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• pp.12-18
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• 1999

• Electrical & Electronic Materials
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• v.10 no.6
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• pp.608-625
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• 1997

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.510-513
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• 2004

This paper represents the response surface model for the cell gap on the flexible liquid crystal display (LCD) process. Using response surface methodology (RSM). D-optimal design is carried out to build the design space and the cell gap is characterized by the quadratic model. The statistical analysis is used to verify the response surface model. This modeling technique can predict the characteristics of the desired response, cell gap, varying with process conditions.

• 한국정보디스플레이학회:학술대회논문집
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• 2004.08a
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• pp.141-144
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• 2004

A QVGA active-matrix backplane is produced on a 25${\mu}m$ thin plastic substrate. A 4-mask photolithographic process is used. The insulator layer and the semiconductor layer are organic material processed from solution. This backplane is combined with the electrophoretic display effect supplied by SiPix and E ink, resulting in an electronic paper display with a thickness of only 100${\mu}m$. This is world's thinnest active-matrix display ever made.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.722-725
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• 2008

In this paper, we propose a new approach for fast generation of CGHs of a 3-D object by using the run-length encoding and N-LUT methods. In this approach, object points to be involved in calculation of the CGH pattern can be dramatically reduced and as a result a significant increase of computational speed can be obtained.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.798-801
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• 2007

For lower power and smaller size with higher image quality, it is desirable to have more units integrated on a display panel. It needs careful design considerations in selecting CMOS, SOP or PCB. An experimental display system is designed and power and delay considering chip area, data rates and bus width are analyzed for all technology combinations to obtain optimum design methodologies.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08a
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• pp.806-809
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• 2007

SRAM cell array and peripheral circuits on display panel are designed using LTPS process. To overcome low yield of SOP, high speed parallel fault detection circuitry for memory cells is designed at local I/O lines with minimal overhead for efficient memory cell redundancy replacement. Normal read/write and parallel test read/write are simulated and verified.