• 제목/요약/키워드: electronic current

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변형된 벨리필 구조와 전하펌프 커패시터가 결합되어 필라멘트 예열기능과 역률개선능력을 가진 형광등용 전자식 안정기 (Electronic Ballast with Modified Valley fill and Charge Pump Capacitor for Prolonged Filaments Preheating and Power Factor Correction)

  • 채균;류태하;조규형
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 F
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    • pp.2798-2800
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    • 1999
  • A new circuit, modified valley fill (MVF) combined with resonant inductor of the self-excited resonant inverter and charge pump capacitors(CPCs), is presented to achieve high PF electronic ballast providing sufficient preheat current to lamp filaments for soft start maintaining low DC bus voltage. The MVF can adjust the valley voltage higher than half the peak line voltage. The CPCs draw the current from the input line to make up the current waveform during the valley interval. The measured PF and THD are 0.99 and 12%, respectively. The lamp current CF is also acceptable in the proposed circuit. The proposed circuit is suitable for implementing cost-effective electronic ballast.

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철심 코어형 전자식 영상 변류기 개발 (Development of the Iron-cored Electronic Zero-Phase Current Transformer)

  • 강용철;김연희;장성일;박종민;최정환;김용균;이병성;송일근
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2008년도 제39회 하계학술대회
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    • pp.140-141
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    • 2008
  • Generally, an iron-cored instrument transformer has differences between the primary current and the secondary current transformer due to the hysteresis characteristics of the core. The errors of the instrument transformer can be removed by using a compensating algorithm. This paper describes the iron-cored electronic zero-phase current transformer(EZCT) having a compensating algorithm that removes the effects of the hysteresis characteristics of the iron-core. This product composes an iron-cored ZCT and an intelligent electronic device(IED) ported the compensating algorithm. The test results shows that the innovative new product can improve the performance of the conventional ZCT.

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리니어펄스모터의 제어 성능 향상을 위한 신경 회로망을 이용한 전류 제어기 설계 (Design of Current Controller for Performance Improvement of Linear Pulse Motor Using Neural Networks)

  • 박종범;박정일;이석규
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 B
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    • pp.486-489
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    • 1998
  • In this paper, we introduced the neural network to reduce force ripple of current controller for a linear pulse motor. In general, conventional position controllers of linear pulse motor disregard the modeling error and load variations, which cause inaccuracy in position control. The proposed current controller based on neural network teaming modifies the current commands in order to reduce force ripple due to these factors. The experiment results show that the proposed controller works efficiently for accurate position control of linear pulse motor.

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동기 리럭턴스 전동기의 에너지 절감을 위한 효율 최적화 제어 (Efficiency Optimization Control for Energy Saving of Synchronous Reluctance Motor)

  • 이정철;이흥균;정동화
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2001년도 전력전자학술대회 논문집
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    • pp.159-162
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    • 2001
  • This paper is proposed an efficiency optimization operation algorithm for synchronous reluctance motor (SynRM) using current phase angle control technique. The SynRM has to controlled with the optimal current phase angles with load and operation speed variation, to obtain high efficiency over the wide speed ranges. An efficiency optimization condition in SynRM which minimizes the copper and iron losses is derived based on the equivalent circuit model of the machine. The objective of the efficiency optimization control algorithm compensating the optimum current angle, is to seek a combination of d and q-axis current components which provides minimum losses at a certain operating point in steady state. The usefulness of the proposed efficiency optimization control is verified through vector-controlled inverter system with the SynRM.

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A GHz-Level RSFQ Clock Distribution Technique with Bias Current Control in JTLs

  • Cho W.;Lim J.H.;Moon G.
    • 한국초전도ㆍ저온공학회논문지
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    • 제8권2호
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    • pp.17-19
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    • 2006
  • A novel clock distribution technique for pipelined-RSFQ logics using variable Bias Currents of JTLs as delay-medium is newly proposed. RSFQ logics consist of several logic gates or blocks connected in a pipeline structure. And each block has variable delay difference. In the structure, this clock distribution method generates a set of clock signals for each logic blocks with suitable corresponding delays. These delays, in the order of few to tens of pS, can be adjusted through controlling bias current of JTL of delay medium. While delays with resistor value and JJ size are fixed at fabrication stage, delay through bias current can be controlled externally, and thus, is heavily investigated for its range as well as correct operation within current margin. Possible ways of a standard delay library with modular structure are sought for further modularizing Pipelined-RSFQ applications. Simulations and verifications are done through WRSpice with Hypres 3-um process parameters.

1선 지락사고에 대한 배전급 저항형 초전도 한류기의 전류제한특성 (Current Limiting Characteristics of a Resistive SFCL for a Single-line-to-ground Fault in the 22.9 kV System)

  • 최효상;황시돌;현옥배
    • 한국전기전자재료학회논문지
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    • 제14권6호
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    • pp.505-510
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    • 2001
  • We simulated the current limiting characteristics of a resistive superconducting fault current limiter (SFCL) for a single line-to-ground fault in the 22.9 kV system. The transient current during the fault increased to 6.33 kA, 5.80 kA and 3.71 kA without SFCL at the fault angles 0$^{\circ}$, 45$^{\circ}$ and 90$^{\circ}$, respectively, a resistive SFCL limited effectively the fault current to 2.27 kA in a half cycle without any DC components. The maximum quench resistance of an SFCL, 16Ω was suggested to be appropriate to limit the fault current in the 22.9 kV distribution system, considering the operating cooperation of a protective relay and the current limiting performance of an SFCL.

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코일형 한류소자의 교류손실 특성 (AC Loss Characteristic in the Fault Current Limiting Elements of a Coil Type)

  • 류경우;마용호
    • 한국전기전자재료학회논문지
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    • 제18권4호
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    • pp.370-374
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    • 2005
  • AC loss of a superconducting conductor has a strong influence on the economic viability of a superconducting fault current limiter, which offers an attractive means to limit short circuit current in power systems. Therefore, the AC loss characteristics in several fault current limiting elements of a coil type have been investigated experimentally. The test result shows that AC losses measured in the fault current limiting elements depend on arrangement of a voltage lead. The AC loss of a bifilar coil is smallest among the fault current limiting elements of the coil type. The measured AC loss of the bifilar coil is much smaller than that calculated from Norris's elliptical model. However, the loss measured in a meander, which is frequently used in a resistive fault current limiter, agrees well to the theoretical one.

플래시 EEPROM 응용을 위한 산화막 특성 (The Oxide Characteristics in Flash EEPROM Applications)

  • 강창수;김동진;강기성
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2001년도 하계학술대회 논문집
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    • pp.855-858
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    • 2001
  • The stress induced leakage currents of thin silicon oxides is investigated in the VLSI implementation of a self learning neural network integrated circuits using a linearity synapse transistor. The channel current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 41 ${\AA}$, 86${\AA}$, which have the channel width ${\times}$ length 10 ${\times}$1${\mu}$m, 10 ${\times}$0.3${\mu}$m respectively. The stress induced leakage currents will affect data retention in synapse transistors and the stress current, transient current is used to estimate to fundamental limitations on oxide thicknesses. The synapse transistor made by thin silicon oxides has represented the neural states and the manipulation which gaves unipolar weights. The weight value of synapse transistor was caused by the bias conditions. Excitatory state and inhitory state according to weighted values affected the channel current. The stress induced leakage currents affected excitatory state and inhitory state.

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전원전압에 따른 초전도 사고전류제한기의 퀜치속도 분석 (Analysis on Quench Velocity of SFCL dependent on Source Voltage)

  • 임성훈
    • 한국전기전자재료학회논문지
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    • 제20권10호
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    • pp.889-894
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    • 2007
  • We investigated the quench velocity of superconducting fault current limiter (SFCL) dependent on the source voltage. $YBa_2Cu_3O_7$ (YBCO) thin film was used as the current limiting element for SFCL. The analysis on the quench velocity of SFCL is essential to determine the capacity of circuit breaker (CB) or coordinate with CB. Generally, the quench velocity of SFCL is related with the short-circuit current. To change the short-circuit current, in this paper, the amplitude of the power source voltage is adjusted. Through the fault current limiting experiments, the quench velocity of SFCL was confirmed to increase fast as the source voltage increased. On the other hand, the peak limited current was shown to increase with steady rate of increase.

Flexible Rogowski 코일을 이용한 클램프형 전류 센서의 개발 (Development of Clamp Current Meter using a Flexible Rogowski Coil)

  • 장용무;김성일
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 2002년도 추계학술대회 논문집 Vol.15
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    • pp.472-475
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    • 2002
  • A Rogowski coil can measure alternating currents from a few amps to over 1 million amps in a frequency range from less than 0.1 Hz to about lMhz. A Rogowski coil provides an induced output voltage which is proportional to the rate of change of the primary current enclosed by the flexible or the rigid coil-loop. Therefore, it is necessary to integrate the output voltage in order to produce a voltage proportional to the current. Also. it can reproduce the current waveform on an oscilloscope or any type of data acquisition device. This paper describes the practical design of the combination of a Rogowski coil and an integrator which provides a versatile current measuring system to accommodate a wide range of frequencies, current levels and conductor sizes.

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