• 한국전기전자재료학회논문지
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• 제13권5호
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• pp.431-436
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM respectively.

• Transactions on Electrical and Electronic Materials
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• 제6권5호
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• pp.225-228
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• 2005

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 영호남학술대회 논문집
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• pp.301-306
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• 2000

This paper describes on the fabrication of a SOI substrate by SDB technology and electrochemical etch-stop. The surface of the thinned SDB SOI substrate is more uniform than that of grinding or polishing by mechanical method, and this process was found to be a very accurate method for SOI thickness control. During electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential(OCP) point, the passivation potential(PP) point and anodic passivation potential. The surface roughness and the controlled thickness selectivity of the fabricated a SDB SOI substrate were evaluated by using AFM and SEM, respectively.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2000년도 춘계학술대회논문집A
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• pp.792-796
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• 2000

With the development of micro machining, it becomes an important part to fabricate an electrode which has tens of ${\mu}m$ or less. There are two methods to get a narrow hole; non-contact type such as EDM(Electro-discharge machining) and contact type such as punching. A punch which has a tapered shape with a cylindrical tip is fabricated in this paper. To make this punch, a method which was used to fabricate a cylindrical shape by electrochemical process was applied. The control factors for the shape and their limits are verified through an experiment.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1999년도 추계학술대회 논문집
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• pp.362-365
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• 1999

This paper describes on thinning SDB SOI substrates by SDB technology and electrochemical etch-stop. The surface of the fabricated SDB SOI substrates is more uniform than that grinding or polishing by mechanical method, and this process is possible to accurate SOI thickness control. During Electrochemical etch-stop, leakage current versus voltage curves were measured for analysis of the open current potential (OCP) point and the passivation potential (PP) poin and determinated to anodic substrates were analyzed by using AFM and SEM, respectivelv.

• Transactions on Electrical and Electronic Materials
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• 제7권3호
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• pp.108-111
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• 2006

The oxidizer-induced corrosion state and microstructure of surface passive metal-oxide layer greatly influenced on the removal rate of tungsten film according to the slurry chemical composition of different mixed oxidizers. In this paper, the actual polishing mechanism and pH-potential equilibrium diagram obtained from potentiodynamic polarization curve were electrochemically compared. An electrochemical corrosion effect implies that slurries with the highest removal rate (RR) have the high dissolution rate.

• 대한기계학회논문집A
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• 제37권3호
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• pp.319-324
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• 2013

본 연구에서는 CNT-Co 복합체를 이용한 전해-자기(EP-MAP) 복합가공 공정을 개발하였다. CNT-Co 복합체는 높은 강도와 뛰어난 전기적 성질을 가지는 소재이기 때문에 전해-자기 복합가공의 연마재 및 전극으로 적합하다. 전해-자기 복합가공의 시너지 효과를 평가하기 위해서 각 실험조건하에서 특성평가 실험이 수행되었으며, 각 실험인자는 자기력, 전해액, 공구의 회전속도, 전해전압, 간극 등이 있다. 그 결과 CNT-Co 복합체와 화학적 반응이 없는 $NaNO_3$ 가 본 공정의 가장 적절한 전해액으로 선정되었다. 그리고 높은 자기력은 가공중의 CNT-Co 복합체내에 전해액 유동을 방해하는 인자이다. 이로 인해 공작물의 표면상의 가공부위에 열에너지가 상승하게 되고 공작물 표면손상과 피팅현상이 발생하여 가공효율성이 떨어지게 된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.88-88
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• 2007

Chemical mechanical polishing (CMP) 공정은 그 어원에서 알 수 있듯이 슬러리의 화학적인 요소와 웨이퍼에 가해지는 기계적 압력에 의해 결정되는 평탄화 기술이다. 최근, 금속배선공정에서 높은 전도율과 재료의 값이 싸다는 이유로 Cu률 사용하였으나, 디바이스의 구조적 특성을 유지하기 위해 높은 압력으로 인한 새로운 다공성 막(low-k)의 파괴와, 디싱과 에로젼 현상으로 인한 문제점이 발생하게 되었다. 이러한 문제점을 해결하고자, 본 논문에서는 Cu 표면에 Passivation layer를 형성 및 제거하는 개념으로 공정시 연마제를 사용하지 않으며, 낮은 압력조건에서 공정을 수행하기 위해, 전해질의 농도 변화에 따른 선형추의전압전류법과 순환전압전류법을 사용하여 전압활성화에 의한 전기화학적 반응이 어떤 영향을 미치는지 연구하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권3호
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• pp.319-325
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• 2017

Through silicon via (TSV) technology is extensively used in 3D IC integrations. The special structure of the TSV is realized by CMP (Chemically Mechanical Polishing) process with a high Cu removal rate and, low dishing, yielding fine topography without defects. In this study, we investigated the electrochemical behavior of copper slurries with various inhibitors in the Cu CMP process for advanced TSV applications. One of the slurries was carried out for the most promising process with a high removal rate (${\sim}18000{\AA}/Min$ @ 3 psi) and low dishing (${\sim}800{\AA}$), providing good microstructure. The effects of pH value and $H_2O_2$ concentration on the slurry corrosion potential and Cu static etching rate (SER) were also examined. The slurry formula with a pH of 6 and 2% $H_2O_2$, hadthe lowest SER (${\sim}75{\AA}/Min$) and was the best for TSV CMP. A novel Cu TSV CMP process was developed with two CMPs and an additional annealing step after some of the bulk Cu had been removed, effectively improving the condition of the TSV Cu surface and preventing the formation of crack defects by variations in wafer stress during TSV process integration.

• 전기화학회지
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• 제10권2호
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• pp.94-103
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• 2007

반도체 소자의 고속화, 고집적화, 고신뢰성화에 대한 요구는 알루미늄 합금으로부터 구리로의 배선 물질의 변화를 유도하였다. 낮은 비저항과 높은 내열화성을 특징으로 하는 구리는 그 전기적, 재료적 특성이 알루미늄과 상이하여 배선 형성에 있어 새로운 주변 재료와 공법을 필요로 한다. 본 총설에서는 상감공정(damascene process)을 사용하는 다층 구리 배선 공정에 있어 핵심이 되는 구리 전해 도금(electrodeposition) 공정을 중심으로 확산 방지막(diffusion barrier) 및 도전층(seed layer), 바닥 차오름(bottom-up filling)을 위한 전해/무전해 도금용 유기 첨가제, 화학적 기계적 평탄화(chemical mechanical polishing) 및 표면 보호막(capping layer) 기술 등의 금속화 공정에 대한 개요와 개발 이슈를 소개하고 최근의 연구 결과를 통해 구리 배선 공정의 최신 연구 동향을 소개하였다.