• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.254-255
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• 2012

Interest in nano-crystalline silicon (nc-Si) thin films has been growing because of their favorable processing conditions for certain electronic devices. In particular, there has been an increase in the use of nc-Si thin films in photovoltaics for large solar cell panels and in thin film transistors for large flat panel displays. One of the most important material properties for these device applications is the macroscopic charge-carrier mobility. Hydrogenated amorphous silicon (a-Si:H) or nc-Si is a basic material in thin film transistors (TFTs). However, a-Si:H based devices have low carrier mobility and bias instability due to their metastable properties. The large number of trap sites and incomplete hydrogen passivation of a-Si:H film produce limited carrier transport. The basic electrical properties, including the carrier mobility and stability, of nc-Si TFTs might be superior to those of a-Si:H thin film. However, typical nc-Si thin films tend to have mobilities similar to a-Si films, although changes in the processing conditions can enhance the mobility. In polycrystalline silicon (poly-Si) thin films, the performance of the devices is strongly influenced by the boundaries between neighboring crystalline grains. These grain boundaries limit the conductance of macroscopic regions comprised of multiple grains. In much of the work on poly-Si thin films, it was shown that the performance of TFTs was largely determined by the number and location of the grain boundaries within the channel. Hence, efforts were made to reduce the total number of grain boundaries by increasing the average grain size. However, even a small number of grain boundaries can significantly reduce the macroscopic charge carrier mobility. The nano-crystalline or polymorphous-Si development for TFT and solar cells have been employed to compensate for disadvantage inherent to a-Si and micro-crystalline silicon (${\mu}$-Si). Recently, a novel process for deposition of nano-crystralline silicon (nc-Si) thin films at room temperature was developed using neutral beam assisted chemical vapor deposition (NBaCVD) with a neutral particle beam (NPB) source, which controls the energy of incident neutral particles in the range of 1~300 eV in order to enhance the atomic activation and crystalline of thin films at room temperature. In previous our experiments, we verified favorable properties of nc-Si thin films for certain electronic devices. During the formation of the nc-Si thin films by the NBaCVD with various process conditions, NPB energy directly controlled by the reflector bias and effectively increased crystal fraction (~80%) by uniformly distributed nc grains with 3~10 nm size. The more resent work on nc-Si thin film transistors (TFT) was done. We identified the performance of nc-Si TFT active channeal layers. The dependence of the performance of nc-Si TFT on the primary process parameters is explored. Raman, FT-IR and transmission electron microscope (TEM) were used to study the microstructures and the crystalline volume fraction of nc-Si films. The electric properties were investigated on Cr/SiO2/nc-Si metal-oxide-semiconductor (MOS) capacitors.

• Journal of Environmental Impact Assessment
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• v.22 no.2
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• pp.135-145
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• 2013

The recycling of coal bottom ash generated from coal power plants in Korea has been limited due to heterogenous characteristics of the materials. The most common management option for the ash is disposal in landfills (i.e. ash pond) near ocean. The presence of large coarse and fine materials in the ash has prompted the desire to beneficially use it in an application such as fill materials. Prior to reuse application as fill materials, the potential risks to the environment must be assessed with regard to the impacts. In this study, a total of nine test cells with bottom ash samples collected from pretreated bottom ash piles and coal ash pond in a coal-fired power plant were constructed and operated under the field conditions to evaluate the leachability over a period of 210 days. Leachate samples from the test cells were analyzed for a number of chemical parameters (e.g., pH, salinity, electrical conductance, anions, and metals). The concentrations of chemicals detected in the leachate were compared to appropriate standards (drinking water standard) with dilution attenuation factor, if possible, to assess potential leaching risks to the surrounding area. Based on the leachate analysis, most of the samples showed slightly high pH values for the coal ash contained test cells, and contained several ions such as sodium, potassium, calcium, magnesium, chloride, sulfate, and nitrate in relatively large quantities. Three elements (aluminum, boron, and barium) were commonly detected above their respective detection limits in a number of leachate samples, especially in the early leaching period of time. The results of the test cell study indicate that the pollutants in the leachate from the coal ash test cells were not of a major concern in terms of leaching risk to surface water and groundwater under field conditions as fill materials. However, care must be taken in extending these results to actual applications because the results presented in this study are based on the limited field test settings and time frame. Structural characteristics and analysis for coal bottom ash may be warranted to apply the materials to actual field conditions.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.36 no.4
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• pp.457-463
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• 2012

Current refrigerators are designed to have thin doors and walls to facilitate user convenience and increase inner storage space. However, the thin doors and walls gives rise to the problem of dew generation on the outer surface of a refrigerator due to a large critical temperature difference between the outer wall and the room air; So far, an electric heater is commonly used for making the dew to evaporate; in this case, the heater inevitably requires additional electrical power. We propose a new approach to reduce the dew generation in a refrigerator by redesigning the gasket and varying the thickness of the inner case of the refrigerator. The results of simulations performed in this study indicate that the surface temperature in the region where dew was generated was increased by approximately $0.39{\sim}3.07^{\circ}C$ without the use of a heater.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.375-375
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• 2012

Graphene is a sp2-hybridized carbon sheet with an atomic-level thickness and a wide range of graphene applications has been intensely investigated due to its unique electrical, optical, and mechanical properties. In particular, hybrid graphene structures combined with various nanomaterials have been studied in energy- and sensor-based applications due to the high conductivity, large surface area and enhanced reactivity of the nanostructures. Conventional metal-catalytic growth method, however, makes useful applications difficult since a transfer process, used to separate graphene from the metal substrate, should be required. Recently several papers have been published on direct graphene growth on the two dimensional planar substrates, but it is necessary to explore a direct growth of hierarchical nanostructures for the future graphene applications. In this study, uniform graphene layers were successfully synthesized on highly dense dielectric nanowires (NWs) without any external catalysts. We also demonstrated that the graphene morphology on NWs can be controlled by the growth parameters, such as temperature or partial pressure in chemical vapor deposition (CVD) system. This direct growth method can be readily applied to the fabrication of nanoscale graphene electrode with designed structures because a wide range of nanostructured template is available. In addition, we believe that the direct growth growth approach and morphological control of graphene are promising for the advanced graphene applications such as super capacitors or bio-sensors.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.7 s.337
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• pp.27-34
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• 2005

Iterative detection (ID) has proven to be a near-optimal solution for concatenated Finite State Machines (FSMs) with interleavers over an additive white Gaussian noise (AWGN) channel. When perfect channel state information (CSI) is not available at the receiver, an adaptive ID (AID) scheme is required to deal with the unknown, and possibly time-varying parameters. The basic building block for ID or AID is the soft-input soft-output (SISO) or adaptive SISO (A-SISO) module. In this paper, Reduced State SISO (RS-SISO) algorithms have been applied for complexity reduction of the A-SISO module. We show that serially concatenated CPM (SCCPM) with AID has turbo-like performance over fading ISI channels and also RS-A-SISO systems have large iteration gains. Various design options for RS-A-SISO algorithms are evaluated. Recently developed density evolution technique is used to analyze RS-A-SISO algorithms. We show that density evolution technique that is usually used for AWGN systems is also a good analysis tool for RS-A-SISO systems over frequency-selective fading channels.

• Journal of IKEEE
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• v.9 no.2 s.17
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• pp.152-160
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• 2005

A prescaler is an essential building block for PLL-based frequency synthesizers and must satisfy high-speed and low-power characteristics. The design of D-flip flips used in the prescaler implementation is thus critical. Conventional TSPC D-flip flops suffer from glitches, unbalanced propagation delay, and unnecessary charge/discharge at internal nodes in precharge phase, which results in increased power consumption. In this paper a new dynamic D-flip flop is proposed to overcome these problems. Glitches are minimized using discharge suppression scheme, speed is improved by making balanced propagation delay, and low power consumption is achieved by removing unnecessary discharge. The proposed D-flip flop is employed in designing a 128/129 dual-modulus prescaler using $0.18{\mu}m$ CMOS process parameters. The designed prescaler operates up to 5GHz while conventional one can operate up to 4.5GHz under same conditions. It consumes 0.394mW at 4GHz that is a 34% improved result compared with conventional one.

• Journal of IKEEE
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• v.16 no.3
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• pp.217-223
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• 2012

This paper presents design and operational characteristics of 150 MW pulse power system for high current pulse forming network to control trigger time. The system is composed of two capacitor bank modules. Each capacitor bank module consist of a trigger vacuum switch, 9k 33kJ capacitor, an energy dump circuit, a crowbar circuit and a pulse shaping inductor and is connected in parallel. It is controlled by trigger controller to select operational module and determine triggering time. Pspice simulation was conducted about determining parameters of components such as crowbar circuit, capacitor, pulse forming inductor, trigger vacuum switch and predicting results of experiment circuit. The result of the experiment was in good agreement with the result of the simulation. The various current shapes with 300~650 us pulse width is formed by sequential firing time control of capacitor bank module. The maximum current is about 40 kA during simultaneous triggering of two capacitor bank modules. The developed 150 MW pulse power system can be applied to high current pulse power system such as rock fragmentation power sources, Rail gun, Coil gun, nano-powers, high power microwave.

• Journal of IKEEE
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• v.22 no.1
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• pp.162-167
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• 2018

In this paper, we propose a method to classify radar signals according to the jamming technique by applying the machine learning to parameter data extracted from received radar signals. In the present army, the radar signal is classified according to the type of threat based on the library of the radar signal parameters mostly built by the preliminary investigation. However, since radar technology is continuously evolving and diversifying, it can not properly classify signals when applying this method to new threats or threat types that do not exist in existing libraries, thus limiting the choice of appropriate jamming techniques. Therefore, it is necessary to classify the signals so that the optimal jamming technique can be selected using only the parameter data of the radar signal that is different from the method using the existing threat library. In this study, we propose a method based on machine learning to cope with new threat signal form. The method classifies the signal corresponding the new jamming method for the new threat signal by learning the classifier composed of the hidden Markov model and the neural network using the existing library data.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.320-320
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• 2016

Nanocrystalline Carbon thin films have numerous applications in different areas such as mechanical, biotechnology and optoelectronic devices due to attractive properties like high excellent hardness, low friction coefficient, good chemical inertness, low surface roughness, non-toxic and biocompatibility. In this work, we studied the comparison of pure DC power and pulsed DC power in plasma sputtering process of carbon thin films synthesis. Using a close field unbalanced magnetron sputtering system, films were deposited on glass and Si wafer substrates by varying the power density and pulsed DC frequency variations. The plasma characteristics has been studied using the I-V discharge characteristics and optical emission spectroscopy. The films properties were studied using Raman spectroscopy, Hall effect measurement, contact angle measurement. Through the Raman results, ID/IG ratio was found to be increased by increasing either of DC power density and pulsed DC frequency. Film deposition rate, measured by Alpha step measurement, increased with increasing DC power density and decreased with pulsed DC frequency. The electrical resistivity results show that the resistivity increased with increasing DC power density and pulsed DC frequency. The film surface energy was estimated using the calculated values of contact angle of DI water and di-iodo-methane. Our results exhibit a tailoring of surface energies from 52.69 to $55.42mJ/m^2$ by controlling the plasma parameters.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.3
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• pp.53-58
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• 2008

In this study, we fabricated embedded IC (Double Pole Double throw switch chip) polymer substrate and evaluate it for 2.4 GHz WiFi application. The switch chips were laminated using FR4 and ABF(Ajinomoto build up film) as dielectric layer. The embedded DPDT chip substrate were interconnected by laser via and Cu pattern plating process. DSC(Differenntial Scanning Calorimetry) analysis and SEM image was employed to calculate the amount of curing and examine surface roughness for optimization of chip embedding process. ABF showed maximum peel strength with Cu layer when the procuring was $80\sim90%$ completed and DPDT chip was laminated in a polymer substrate without void. An embedded chip substrate and wire-bonded chip on substrate were designed and fabricated. The characteristics of two modules were measured by s-parameters (S11; return loss and S21; insertion loss). Insertion loss is less than 0.55 dB in two presented embedded chip board and wire-bonded chip board. Return loss of an embedded chip board is better than 25 dB up to 6 GHz frequency range, whereas return loss of wire-bonding chip board is worse than 20 dB above 2.4 GHz frequency.