• 한국전기전자재료학회논문지
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• 제34권1호
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• pp.16-20
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• 2021

In this study, we tried finding new materials to improve the stain resistance properties of polymer insulating materials. Using the filtered vacuum arc source (FVAS) with a graphite target source, DLC thin films were deposited on silicon and polymer insulator substrates depending on their thickness to confirm the surface properties, physical properties, and structural properties of the thin films. Subsequently, the possibility of using a DLC thin film as a protective coating material for polymer insulators was confirmed. DLC thin films manufactured in accordance with the thickness of various thin films exhibited a very smooth and uniform surface. As the thin film thickness increased, the surface roughness value decreased and the contact angle value increased. In addition, the elastic modulus and hardness of the DLC thin film slightly increased, and the maximum values of elastic modulus and hardness were 214.5 GPa and 19.8 GPa, respectively. In addition, the DLC thin film showed a very low leakage current value, thereby exhibiting electrical insulation properties.

• 마이크로전자및패키징학회지
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• 제30권2호
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• pp.60-64
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• 2023

본 연구에서는 그래핀 기반 소자의 성능에 영향을 미치는 그래핀과 금속 사이의 전기적 접촉저항 특성을 비교 분석하였다. 화학기상증착법을 이용하여 고품질의 그래핀을 합성하였으며, 전극 물질로 Al, Cu, Ni 및 Ti를 동일한 두께로 그래핀 표면 위에 증착하였다. TLM (transfer length method) 방법을 통해 SiO₂/Si 기판에 전사된 그래핀과 금속의 접촉저항을 측정한 결과, Al, Cu, Ni, Ti의 평균 접촉저항은 각각 345 Ω, 553 Ω, 110 Ω, 174 Ω으로 측정되었다. 그래핀과 물리적 흡착 특성을 갖는 Al와 Cu에 비해 화학적 결합을 형성하는 Ni과 Ti의 경우, 상대적으로 더 낮은 접촉저항을 갖는 것을 확인하였다. 본 연구의 그래핀과 금속의 전기적 특성에 대한 연구 결과는 전극과의 낮은 접촉저항 형성을 통해 고성능 그래핀 기반 전자, 광전자소자 및 센서 등의 구현에 기여할 수 있을 것으로 기대한다.

• 전기학회논문지P
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• 제65권1호
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• pp.53-56
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• 2016

Because of the low pollution resistance of the porcelain electrical insulator itself, in this work the anti-pollution performance of insulator was improved by using the functional coating. The ceramic substrates that components were same as the porcelain electrical insulator were used in this experiment. The functional films were coated on the ceramic substrate by using a spray coating method, and then the coated substrate were annealed under different coating condition such as natural curing and annealing temperature of $200^{\circ}C$, $300^{\circ}C$ and $400^{\circ}C$. Then, the contact angles of the coated surfaces were measured and the minimum angle ($8.3^{\circ}$) was obtained at $400^{\circ}C$. The anti-contamination properties were measured, revealing that as the contact angle decreased, the anti-contamination properties improved. The hardness and adhesion were small at the natural curing condition however the excellent mechanical properties were obtained under higher temperature annealing.

• 한국전기전자재료학회논문지
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• 제24권12호
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• pp.988-991
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• 2011

We fabricated a copper phthalocyanine (CuPc) based field-effect transistor with different device structure as a bottom and top contact FET. Also, we used a $SiO_2$ as a gate insulator and analyzed using a current-voltage (I-V) characteristics of the bottom and top contact CuPc FET device. In order to discuss the channel formation, we were observed the capacitance-gate voltage(C-V) characteristics of the bottom and top contact CuPc FET device.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.151-154
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• 1998

We have investigated a correlation of the electrical properties of the Pd/Ge/Pd/Ti/Au ohmic contact on n-InGaAs with its microstructures for the high temperature application of compound semiconductor devices. The samples were heat-treated by the rapid thermal annealing at various temperatures. In the contact system, moderately good specific contact resistance was obtained even before annealing because of the low metals-InGaAs barrier height, and better ohmic performances were observed by annealing up to 400˚C. But the ohmic performance was degraded after annealing at 450˚C due to the increment of Pd$_2$Ga$\sub$5/ phases.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 C
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• pp.1376-1377
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• 2006

본 연구에서는 고밀도 플라즈마 식각 시스템을 이용하여 contact hole 식각을 연구하였다. 실험은 공정 변수에 따른 식각 특성을 변화를 SEM 분석을 이용하여 보였으며 공정 압력 증가에 따른 contact hole 패턴의 하부 및 측면이 vertical 하지 못한 현상을 볼 수 있었으며 이는 과도한 라디컬 생성으로 인하여 식각 반응 부산물과 폴리머가 식각 패턴 밖으로 탈착되지 못하여 나타나는 것으로 생각되며 하부 bias 전력을 증가시킴으로써 식각 반응 부산물과 폴리머의 탈착을 도와 식각 프로파일 개선에 영향을 줌을 확인하였다. 또한, 본 장비의 낮은 전자온도 등의 특성으로 인하여 PR의 degradation 현상 등이 나타나지 않았다.

• 대한금속재료학회지
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• 제50권10호
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• pp.785-792
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• 2012

A new flip chip structure consisting of interlocking joints locally surrounded by non-conductive adhesive was investigated in order to improve the contact resistance characteristics and prevent the parasitic capacitance increase. The average contact resistance of the interlocking joints was substantially reduced from $135m{\Omega}$ to $79m{\Omega}$ by increasing the flip chip bonding pressure from 85 MPa to 185 MPa. Improvement of the contact resistance characteristics at higher bonding pressure was attributed not only to the increased contact area between Cu chip bumps and Sn pads, but also to the severe plastic deformation of Sn pads caused during formation of the interlocking-joint structure. The parasitic capacitance increase due to the non-conductive adhesive locally surrounding the flip chip joints was estimated to be as small as 12.5%.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 추계학술대회 논문집 Vol.16
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• pp.167-171
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• 2003

We report the material and electrical properties of $CoSi_2$ and $NiSi_2$contacts to n-type 4H-SiC depending on the post-annealing and the metal covering conditions. The Ni and Co silicides are deposited by RF sputtering with Ni/Si/Ni and Co/Si/Co films separately deposited on 4H-SiC substrates. The deposited films are annealed at $800\;^{\circ}C$ in $Ar:H_2$ (9:1) gas ambient. Results of the specific surface resistivity measurements show that the resistivity of the Co-based metal contact was the one order lower than that of the Ni-based contact. The specific contact resistance was measured by a transmission line technique, and the specific contact resistivity of $1.5{\times}10^{-6}\;{\Omega}\;cm^2$ is obtained for Co/Si/Co metal structures after a two-step annealing; at $550\;^{\circ}C$ for 10 min and $800\;^{\circ}C$ for 3min. The physical properties of the contacts were examined by using XRD and AES, and the results indicate that the Co-based metal contacts have better structural stability of silicide phases formed after the high temperature annealing.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2006년도 하계학술대회 논문집 Vol.7
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• pp.321-322
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• 2006

The electrical properties of PZT thin film capacitor on TiN/W plug structure were investigated for high density ferroelectric memory devices. In order to enhance the ferroelectric properties of PZT capacitor, the process conditions of bottom electrodes were optimized. The fabricated PZT capacitor on TiN/W plug showed good remanent polarization, leakage current, and contact resistance of TiN/W plug, which were $33\;{\mu}C/cm^2$, $1.2{\times}10^{-6}\;A/cm^2$, and 5.3 ohm/contact, respectively.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.404-405
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• 2007

Tin-doped indium thin film is outstanding material among transparent Conductive Oxide (TCO) materials. ITO thin films show a low electrical resistance(<$10^{-4}\;[{\Omega}{\cdot}m]$) and high transmittance(>80%) in the visible range. ITO thin films usually have been deposited on the glass substrate. In order to apply flexible display, the substrate should have the ability to bend and be deposited without substrate heat. Also properties of ITO thin film depend on what kind of substrate. In this study, we prepared ITO thin film on the polycarbonate (PC) substrate by using Facing Target Sputtering (FTS) system. Before deposition of ITO thin film, PC substrate took plasma surface treatment. The electrical and surface properties of as-deposited thin films were investigated by Hall Effect measurement, UV/VIS spectrometer and the surface property of substrate is investigated by Contact angle measurement.