• Korean Journal of Materials Research
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• v.27 no.2
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• pp.107-112
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• 2017

The BCBJ (Back Contact and Back Junction) or back-lit solar cell design eliminates shading loss by placing the pn junction and metal electrode contacts all on one side that faces away from the sun. However, as the electron-hole generation sites now are located very far from the pn junction, loss by minority-carrier recombination can be a significant issue. Utilizing Medici, a 2-dimensional semiconductor device simulation tool, the interdependency between the substrate thickness and the minority-carrier recombination lifetime was studied in terms of how these factors affect the solar cell power output. Qualitatively speaking, the results indicate that a very high quality substrate with a long recombination lifetime is needed to maintain the maximum power generation. The quantitative value of the recombination lifetime of minority-carriers, i.e., electrons in p-type substrates, required in the BCBJ cell is about one order of magnitude longer than that in the front-lit cell, i.e., $5{\times}10^{-4}sec$ vs. $5{\times}10^{-5}sec$. Regardless of substrate thickness up to $150{\mu}m$, the power output in the BCBJ cell stays at nearly the maximum value of about $1.8{\times}10^{-2}W{\cdot}cm^{-2}$, or $18mW{\cdot}cm^{-2}$, as long as the recombination lifetime is $5{\times}10^{-4}s$ or longer. The output power, however, declines steeply to as low as $10mW{\cdot}cm^{-2}$ when the recombination lifetime becomes significantly shorter than $5{\times}10^{-4}sec$. Substrate thinning is found to be not as effective as in the front-lit case in stemming the decline in the output power. In view of these results, for BCBJ applications, the substrate needs to be only mono-crystalline Si of very high quality. This bars the use of poly-crystalline Si, which is gaining wider acceptance in standard front-lit solar cells.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.568-568
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• 2013

현재 태양전지 도핑 공정은 퍼니스와 레이저 도핑공정이 주요공정으로 사용되고 있다. 퍼니스 도핑 공정은 POCl3 가스를 도펀트로 사용하여 확산 공정으로 진행한다. 퍼니스 도핑공정은 고가의 장비와 유독 가스사용으로 인한 처리 문제, 웨이퍼의 국부적인 부분에 고농도 도핑을 하는데는 제한적이다. 레이저를 사용한 선택적 도핑의 경우 고가의 레이저장비가 요구되어진다. 본 연구는 기존 도핑공정 문제점을 보완한 저가이면서 새로운 구조의 대기압 플라즈마 제트를 개발하였고, 이를 통한 인산을 사용하여 선택적 도핑에 관한 연구를 하였다. 대기압 플라즈마 제트는 Ar 가스를 주입하여 저주파(1 kHz~100 kHz) 전원을 인가하여 플라즈마를 발생시키는 구조로 제작하였다. 웨이퍼는 태양전지용 P-type shallow 도핑된(120 Ohm/square) 웨이퍼를 사용하였고, 도펀트는 스핀코터를 사용하여 도포를 하였다. 인산의 농도는 10%, 50%, 85%를 사용하였다. 플라즈마 발생 전류는 70 mA, 120 mA에서 실험을 하였다. 대기압 플라즈마 처리시간은 30 s, 90 s, 150 s 처리하여 도핑공정을 진행하였고, 도핑 프로파일은 SIMS (Secondary Ion Mass Spectroscopy)측정을 통하여 분석을 진행하였다. 도펀트의 농도와 전류가 높아짐에 따라서, 도핑 처리시간이 길어짐에 따라서 도핑 깊이가 깊어짐을 확인하였다. 도핑 프로파일을 분석하여 Effective carrier lifetime을 얻었으며, 도펀트 농도가 증가하거나 도핑 처리시간이 길어짐에 따라서 Effective carrier lifetime 낮아짐을 확인하였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.2
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• pp.120-124
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• 2000

In this paper, the effects of trap distribution on switching characteristis of a lateral insulated gate bipolar transistor (LIGBT) are investigated. The simulations are performed in order to to analyze the effect of the positon, width and concentration of trap distribution model with a reduced minority carrier lifetime using 2D device simulator MEDICI. The turn off time for the proposed LIGBT model A with the trap injection is 0.8$mutextrm{s}$. These results indicate the improvement of about 2 times compared with the conventional LIGBT. It is shown that the trap distribution model is very effective to reduce the turn-off time with a little increasing of on-state voltage drop.

• Transactions on Electrical and Electronic Materials
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• v.10 no.3
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• pp.75-79
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• 2009

An intrinsic silicon thin film passivation layer is deposited by the microwave remote-plasma enhanced chemical vapor deposition at temperature of $175^{\circ}C$ and various gas ratios for solar cell applications. The good quality amorphous silicon films were formed at silane $(SiH_4)$ gas flow rates above 15 seem. The highest effective carrier lifetime was obtained at the $SiH_4$, flow rate of 20 seem and the value was about 3 times higher compared with the bulk lifetime of 5.6 ${\mu}s$ at a fixed injection level of ${\Delta}n\;=\;5{\times}10^{14}\;cm^{-3}$. An annealing treatment was performed and the carrier life times were increased approximately 5 times compared with the bulk lifetime. The optimal annealing temperature and time were obtained at 250 $^{\circ}C$ and 60 sec respectively. This indicates that the combination of the deposition of an amorphous thin film at a low temperature and the annealing treatment contributes to the excellent surface and bulk passivation.

• Journal of the Korean Society for Precision Engineering
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• v.19 no.6
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• pp.145-154
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• 2002

CMP (Chemical mechanical polishing) process was used to control the fine grinding process induced mechanical damage of Cz Silicon wafer. Characterization of mechanical damage was carried out using Nomarski microscope, magic mirror and also using angle lapping and lifetime scanner evaluation after heat treatment. Magic mirror and lifetime scanner were very useful for the residual damage pattern characterization and CMP process was effective on the reduction of fine grinding induced mechanical damage.

• Journal of the Korean Ceramic Society
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• v.51 no.3
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• pp.197-200
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• 2014

We investigated the influence of blistering on $Al_2O_3$/SiON stacks and $Al_2O_3$/SiNx:H stacks passivation layers. $Al_2O_3$ film provides outstanding Si surface passivation quality. $Al_2O_3$ film as the rear passivation layer of a p-type Si solar cell is usually stacked with a capping layer, such as $SiO_2$, SiNx, and SiON films. These capping layers protect the thin $Al_2O_3$ layer from an Al electrode during the annealing process. We compared $Al_2O_3$/SiON stacks and $Al_2O_3$/SiNx:H stacks through surface morphology and minority carrier lifetime after annealing processes at $450^{\circ}C$ and $850^{\circ}C$. As a result, the $Al_2O_3$/SiON stacks were observed to produce less blister phenomenon than $Al_2O_3$/SiNx:H stacks. This can be explained by the differences in the H species content. In the process of depositing SiNx film, the rich H species in $NH_3$ source are diffused to the $Al_2O_3$ film. On the other hand, less hydrogen diffusion occurs in SiON film as it contains less H species than SiNx film. This blister phenomenon leads to an increase insurface defect density. Consequently, the $Al_2O_3$/SiON stacks had a higher minority carrier lifetime than the $Al_2O_3$/SiNx:H stacks.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.46.1-46.1
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• 2010

Surface passivation of crystalline silicon(c-Si) surface with a-Si:H thin films has been investigated by using quasi-steady-state photo conductance(QSSPC) measurements. Analyzing the influence of a-Si:H film thickness, process gas ratio, deposition temperature and post annealing temperature on the passivation properties of c-Si, we optimized the passivation conditions at the substrate temperature of $200-250^{\circ}C$. Best surface passivation has been obtained by post-deposition annealing of a-Si:H film layer. Post annealing around the deposition temperature was sufficient to improve the surface passivation for silicon substrates. We obtained effective carrier lifetimes above 5.5 ms on average.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.8
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• pp.463-467
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• 2000

In this paper, the new LIGBT structures with trap injection are proposed to improve switching characteristics of the conventional SOI LIGBT. The Simulations are performed in order to investigate the effects of the positiion, whidth and concentration of trap injection region with a reduced minority carrier lifetime using 2D device simulator MEDICI. Their electrical characteristics are analyzed and the optimum design parameters are extracted. As a result of simulation, the turn off time for the model A with the trap injection is $0.78\mus$. These results indicate the improvement of about 2 times compared with the conventional SOI LIGBT because trap injection prevents minority carriers which is stored in the n-drift region during turn off switching. The latching current is $1.5\times10^{-4}A/\mum$ and forward blocking voltage is 168V which are superior to those of conventional structure. It is shown that the trap injection is very effective to reduce the turn off time with a little increasing of on-state voltage drop if its design and process parameters are optimized.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.243-246
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• 2001

Thyristor devices have 3-dimensional complicated structure and were sensitive to temperature characteristics. Therefore, it was difficult to optimize thyristor devices design. We have to consider many design parameter to characterize, and trade-off relations. The important parameters to design thyristor devices are cathode structure, effective line width, cathode-emitter shunt structure, gate structure, doping profile and carrier lifetime. So, we must consider that these design parameters were not acted separately. However, there are many difficulties to determine optimized design parameters by experiment. So, We used specific design software to design thyristor devices, and estimated the thyristor devices characteristics.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.406-406
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• 2016

To get high efficiency n-type crystalline silicon solar cells, passivation is one of the key factor. Tunnel oxide (SiO2) reduce surface recombination as a passivation layer and it does not constrict the majority carrier flow. In this work, the passivation quality enhanced by different chemical solution such as HNO3, H2SO4:H2O2 and DI-water to make thin tunnel oxide layer on n-type crystalline silicon wafer and changes of characteristics by subsequent annealing process and firing process after phosphorus doped amorphous silicon (a-Si:H) deposition. The tunneling of carrier through oxide layer is checked through I-V measurement when the voltage is from -1 V to 1 V and interface state density also be calculated about $1{\times}1012cm-2eV-1$ using MIS (Metal-Insulator-Semiconductor) structure . Tunnel oxide produced by 68 wt% HNO3 for 5 min on $100^{\circ}C$, H2SO4:H2O2 for 5 min on $100^{\circ}C$ and DI-water for 60 min on $95^{\circ}C$. The oxide layer is measured thickness about 1.4~2.2 nm by spectral ellipsometry (SE) and properties as passivation layer by QSSPC (Quasi-Steady-state Photo Conductance). Tunnel oxide layer is capped with phosphorus doped amorphous silicon on both sides and additional annealing process improve lifetime from $3.25{\mu}s$ to $397{\mu}s$ and implied Voc from 544 mV to 690 mV after P-doped a-Si deposition, respectively. It will be expected that amorphous silicon is changed to poly silicon phase. Furthermore, lifetime and implied Voc were recovered by forming gas annealing (FGA) after firing process from $192{\mu}s$ to $786{\mu}s$. It is shown that the tunnel oxide layer is thermally stable.