• Proceedings of the SAREK Conference
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• 2008.06a
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• pp.919-924
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• 2008

Power consumption in the building thermal load could be the sum of the building fabric conduction load, building ventilation convection load and other such as radiation loss load. Dynamic Breathing Building (DBB) is the state-of-the-art to improve the wall insulation and indoor air quality(IAQ) performance as making air flow through the wall. This heat recovery type DBB contributes the power consumption saving due to the improved dynamic U-value. KIER twin test cell with static insulation(SI) and dynamic insulation(DI) at KIER was developed to test building power consumption at the real outside conditions. Then, the actual results were compared with the theory to predict the power consumption at the KIER twin test cell and introduced the building new radiation loss factor $\alpha$ to explain the difference between the both the theory and the actual case. As the results, the power consumption at the breathing DI wall building could saved 10.8% at the 2ACH(Air change per hour) compared with conventional insulation. The building radiation loss factor $\alpha$ for this test condition to calibrate the actual test was 0.55 in the test condition.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.78-84
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• 2012

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.10 no.2
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• pp.74-79
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• 2011

The goal of this research is to reduce dynamic and static power consumption for a low power cache system. The proposed cache can achieve a low power consumption by using a drowsy and a way prediction mechanism. For reducing the static power, the drowsy technique is used at 4-way set associative cache. And for reducing the dynamic energy, one among four ways is selectively accessed on the basis of information in the Way-Line Prediction Unit (WLPU). This prediction mechanism does not introduce any additional delay though prediction misses are occurred. The WLPU can effectively reduce the performance overhead of the conventional drowsy caching by waking only a drowsy cache line and one way in advance. Our results show that the proposed cache can reduce the power consumption by about 40% compared with the 4-way drowsy cache.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.6
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• pp.1039-1046
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• 2007

This paper presents the analysis for power consumption, mechanical vibration and acoustic noise characteristics of the Coreless and Slotless Brushless DC motor in Digital Lightening Processor(DLP) Motor with the Air-Dynamic Bearing. The Coreless BLDC motor has not the stator yoke as well as the stator slot to remove the unbalance force by the interaction between the stator yoke and Air-Dynamic Bearing clearance. The assembling tolerance and the processing error make the air-gap difference between the magnet and the stator yoke .which occurs the unbalanced electro-magnetic force in the Slotless BLDC motor. It imposes the air-dynamic bearing on the disturbance force and makes the Air-Dynamic Bearing vibrated and noised. Also, The attractive force between the magnet and the silicon steel stator yoke increases the power consumption. In this paper, the power consumption, mechanical vibration and acoustic noise of the Coreless BLDC motor and the Slotless BLDC motor with the silicon steel stator yoke are simulated, analyzed, and tested using the manufactured proto-type motors with Air-Dynamic bearing. The simulated and tested results present that the Coreless BLDC motor without the silicon steel stator yoke has the lower mechanical vibration and noise ,and lower power consumption than the Slotless BLDC motor with the silicon steel stator yoke in Digital Lightening Processor Motor with Air-Dynamic Bearing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.2
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• pp.47-54
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• 2004

Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals increase, power consumption associated with interconnects is ever-increasing. In case of clock trees, particularly power consumption associated with interconnects is over 30％ of total power consumption. Hence, an efficient method to compute power consumption of interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power consumption of interconnects. We propose a new reduced-order model to estimate power consumption of large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power consumption of whole interconnects can be approximated, and propose an analytical method to compute the power consumption. The results applying the proposed method to various RC networks show that average relative error is 1.86％ and maximum relative error is 9.82％ in comparison with HSPICE results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.3
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• pp.586-594
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• 2014

Maximizing the operating time by reducing the power consumption is important factor to operate sensor network under water networks. For efficient power consumption, dynamic voltage scaling method is available. This method operates low frequency when there is no workload. In case of abundant workload, high frequency operation completes hard work within short time, reducing power consumption. For this reason, complex cryptography should be computed in high frequency. In this paper, we apply dynamic voltage scaling method to cryptography and show performance evaluation. With this result, we can reduce power consumption for cryptography in under water communication.

• Journal of Electrical Engineering and Technology
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• v.4 no.2
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• pp.255-265
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• 2009

This paper presents the acoustic noise and mechanical vibration reduction of a coreless brushless DC motor with an air dynamic bearing used in a digital lightening processor. The coreless brushless DC motor does not have a stator yoke or stator slot to remove the unbalanced force caused by the interaction between the stator yoke and the rotor magnet. An unbalanced force makes slotless brushless DC motors vibrate and mechanically noisy, and the attractive force between the magnet and the stator yoke increases power consumption. Also, when a coreless brushless DC motor is driven by a $120^{\circ}$ conduction type inverter, high frequency acoustic noise occurs because of the peak components of the phase currents caused by small phase inductance and large phase resistance. In this paper, a core-less brushless DC motor with an air dynamic bearing to remove mechanical vibration and to reduce power consumption is applied to a digital lightening processor. A $180^{\circ}$ conduction type inverter drives it to reduce high frequency acoustic noise. The applied methods are simulated and tested using a manufactured prototype motor with an air dynamic bearing. The experimental results show that a coreless brushless DC motor has characteristics of low power consumption, low mechanical vibration, and low high frequency acoustic noise.

• Journal of Digital Contents Society
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• v.10 no.2
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• pp.217-223
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• 2009

In order to decrease the power consumption in Embedded Linux environment based on XScale PXA255, We produce the device driver of DFS(Dynamic Frequency Scaling) technique, design and implement the middleware DFM(Dynamic Frequency Management) to scale the power of embedded target board with porting this device drive, suggest the method to reduce the Embedded system's power consumption.

• Electronics and Telecommunications Trends
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• v.35 no.2
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.179-182
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• 2000

Adiabatic dynamic CMOS logic circuits, which are called ADCL circuits, promise us to implement low power logic circuits. Since the power supply source for ADCL circuits had not been developed, we proposed a power supply circuit for them. It is shown experimentally that by using the power supply circuit ADCL circuits can work with lower power consumption than conventional static CMOS circuit. In this paper, the power supply circuit is improved so that the power consumption can be reduced. Also, it is shown by some experiments that by using the circuit, ADCL circuits can work with lower power consumption than before Improving.