• 대한설비공학회:학술대회논문집
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• 대한설비공학회 2008년도 하계학술발표대회 논문집
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• pp.919-924
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• 2008

Power consumption in the building thermal load could be the sum of the building fabric conduction load, building ventilation convection load and other such as radiation loss load. Dynamic Breathing Building (DBB) is the state-of-the-art to improve the wall insulation and indoor air quality(IAQ) performance as making air flow through the wall. This heat recovery type DBB contributes the power consumption saving due to the improved dynamic U-value. KIER twin test cell with static insulation(SI) and dynamic insulation(DI) at KIER was developed to test building power consumption at the real outside conditions. Then, the actual results were compared with the theory to predict the power consumption at the KIER twin test cell and introduced the building new radiation loss factor $\alpha$ to explain the difference between the both the theory and the actual case. As the results, the power consumption at the breathing DI wall building could saved 10.8% at the 2ACH(Air change per hour) compared with conventional insulation. The building radiation loss factor $\alpha$ for this test condition to calibrate the actual test was 0.55 in the test condition.

• Journal of information and communication convergence engineering
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• 제10권1호
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• pp.78-84
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• 2012

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.

• 정보통신설비학회논문지
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• 제10권2호
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• pp.74-79
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• 2011

The goal of this research is to reduce dynamic and static power consumption for a low power cache system. The proposed cache can achieve a low power consumption by using a drowsy and a way prediction mechanism. For reducing the static power, the drowsy technique is used at 4-way set associative cache. And for reducing the dynamic energy, one among four ways is selectively accessed on the basis of information in the Way-Line Prediction Unit (WLPU). This prediction mechanism does not introduce any additional delay though prediction misses are occurred. The WLPU can effectively reduce the performance overhead of the conventional drowsy caching by waking only a drowsy cache line and one way in advance. Our results show that the proposed cache can reduce the power consumption by about 40% compared with the 4-way drowsy cache.

• 전기학회논문지
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• 제56권6호
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• pp.1039-1046
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• 2007

This paper presents the analysis for power consumption, mechanical vibration and acoustic noise characteristics of the Coreless and Slotless Brushless DC motor in Digital Lightening Processor(DLP) Motor with the Air-Dynamic Bearing. The Coreless BLDC motor has not the stator yoke as well as the stator slot to remove the unbalance force by the interaction between the stator yoke and Air-Dynamic Bearing clearance. The assembling tolerance and the processing error make the air-gap difference between the magnet and the stator yoke .which occurs the unbalanced electro-magnetic force in the Slotless BLDC motor. It imposes the air-dynamic bearing on the disturbance force and makes the Air-Dynamic Bearing vibrated and noised. Also, The attractive force between the magnet and the silicon steel stator yoke increases the power consumption. In this paper, the power consumption, mechanical vibration and acoustic noise of the Coreless BLDC motor and the Slotless BLDC motor with the silicon steel stator yoke are simulated, analyzed, and tested using the manufactured proto-type motors with Air-Dynamic bearing. The simulated and tested results present that the Coreless BLDC motor without the silicon steel stator yoke has the lower mechanical vibration and noise ,and lower power consumption than the Slotless BLDC motor with the silicon steel stator yoke in Digital Lightening Processor Motor with Air-Dynamic Bearing.

• 대한전자공학회논문지SD
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• 제41권2호
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• pp.47-54
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• 2004

현재까지 연결선을 타이밍(timing) 관점에서 해석하려는 시도들은 많았지만, 전력 소모의 관점에서 해석하려는 시도는 많지 않았다. 그러나 지금은 연결선의 저항 성분과 신호의 상승 시간이 점차 증가하는 추세에 따라 회로 연결선에서의 전력 소모가 증가하고 있는 시점이다. 특히, 클럭 신호선의 경우 칩 전체 전력 소모 중 30％ 이상을 차지하고 있다. 따라서 회로 연결선에서의 전력 소모를 효과적으로 계산하는 방법이 필요하며, 본 논문에서는 회로 연결선의 동적 전력 소모를 계산하는 간단하면서도 정확한 방법을 제시하고자 한다. 사이즈가 큰 연결선의 동적 전력 소모를 계산하기 위한 축소 모형을 제안하고, 이 축소모형을 구성하는 방법을 제시한다. 제안한 축소 모형의 해석을 통해 연결선 전체의 동적 전력 소모를 근사할 수 있음을 보이고, 이를 간단히 계산하는 방법을 제안 하고자 한다. 노드 수 100∼1000개까지 RC 회로에 대해 제안한 방법을 적용한 결과 연결선의 전력 소모는 HSPICE에 비해 1.86％의 평균 상대 오차 및 9.82％의 최대 상대 오차를 보였다.

• 한국정보통신학회논문지
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• 제18권3호
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• pp.586-594
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• 2014

수중 통신 상에서 가장 중요한 요소는 한정된 전원을 보다 효율적으로 소모하여 운영 가능 시간을 최대화하는데 있다. 보다 효율적인 전압 소모를 위해 적용 가능한 기법으로는 동적 전압 스케일 기법이 있다. 해당 기법은 평상시에는 낮은 주파수로 동작하여 대기 전력을 최소화하며 복잡한 연산을 수행하는 경우에는 빠른 주파수로 계산함으로써 전체 소모되는 전력량을 줄인다. 복잡한 암호화 연산의 경우 빠른 주파수로 연산을 하는 것이 보다 효율적이다. 본 논문에서는 다양한 센서 상에서의 암호화 기법에 동적 전압 스케일 기법을 적용한 결과를 보여 줌으로써 수중 통신 상에서 적합한 저전력 암호화 방안에 대해 살펴본다.

• Journal of Electrical Engineering and Technology
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• 제4권2호
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• pp.255-265
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• 2009

This paper presents the acoustic noise and mechanical vibration reduction of a coreless brushless DC motor with an air dynamic bearing used in a digital lightening processor. The coreless brushless DC motor does not have a stator yoke or stator slot to remove the unbalanced force caused by the interaction between the stator yoke and the rotor magnet. An unbalanced force makes slotless brushless DC motors vibrate and mechanically noisy, and the attractive force between the magnet and the stator yoke increases power consumption. Also, when a coreless brushless DC motor is driven by a $120^{\circ}$ conduction type inverter, high frequency acoustic noise occurs because of the peak components of the phase currents caused by small phase inductance and large phase resistance. In this paper, a core-less brushless DC motor with an air dynamic bearing to remove mechanical vibration and to reduce power consumption is applied to a digital lightening processor. A $180^{\circ}$ conduction type inverter drives it to reduce high frequency acoustic noise. The applied methods are simulated and tested using a manufactured prototype motor with an air dynamic bearing. The experimental results show that a coreless brushless DC motor has characteristics of low power consumption, low mechanical vibration, and low high frequency acoustic noise.

• 디지털콘텐츠학회 논문지
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• 제10권2호
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• pp.217-223
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• 2009

XScale PXA255 기반 Embedded Linux 환경에서 전력 소비를 줄이기 위해 DFS(Dynamic Frequency Scaling) 기법의 디바이스 드라이버를 제작하고 이 디바이스 드라이버가 포팅되어 있는 임베디드 타겟보드의 전력을 관리하기 위한 미들웨어 DFM(Dynamic Frequency Management)를 설계하고 구현하여 임베디드 시스템의 전력 소비를 감소하는 방법을 제시한다.

• 전자통신동향분석
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• 제35권2호
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• pp.69-78
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• 2020

Small portable devices such as mobile phones and laptops currently display a trend of high power consumption owing to their characteristics of high speed and multifunctionality. Low-power SoC design is one of the important factors that must be considered to increase portable time at limited battery capacities. Popular low power SoC design techniques include clock gating, multi-threshold voltage, power gating, and multi-voltage design. With a decreasing semiconductor process technology size, leakage power can surpass dynamic power in total power consumption; therefore, appropriate low-power SoC design techniques must be combined to reduce power consumption to meet the power specifications. This study examines several low-power SoC design trends that reduce semiconductor SoC dynamic and static power using EDA tools. Low-power SoC design technology can be a competitive advantage, especially in the IoT and AI edge environments, where power usage is typically limited.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 ITC-CSCC -1
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• pp.179-182
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• 2000

Adiabatic dynamic CMOS logic circuits, which are called ADCL circuits, promise us to implement low power logic circuits. Since the power supply source for ADCL circuits had not been developed, we proposed a power supply circuit for them. It is shown experimentally that by using the power supply circuit ADCL circuits can work with lower power consumption than conventional static CMOS circuit. In this paper, the power supply circuit is improved so that the power consumption can be reduced. Also, it is shown by some experiments that by using the circuit, ADCL circuits can work with lower power consumption than before Improving.