• The Transactions of the Korean Institute of Electrical Engineers D
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• v.51 no.3
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• pp.100-107
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• 2002

In this paper, we propose an expert system for electronic interlocking which enhances the safty, efficiency and expanability of the existing system by designing real-time interlocking control based on the interlocking table automatically generated using artificial intelligence approach. The expert system consists of two parts; an interlocking table generation part and a real-time interlocking control part. The former generates automatically the interlocking relationship of all possible routes by searching dynamically the station topology which is obtained from station database. On the other hand, the latter controls the status of station facilities in real-time by applying the generated interlocking relationship to the signal facilities such as signal devices, points, track circuits for a given route. The expert system is implemented in C language which is suitable to implement the interlocking table generation part using the dynamic memory allocation technique. Finally, the effectiveness of the expert system is proved by simulating for the typical station model.

• Speech Sciences
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• v.14 no.4
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• pp.157-167
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• 2007

In this paper, we implemented a single-chip speech recognizer using the TMS320C2000 DSPs. For this implementation, we had developed very small-sized speaker-dependent recognition engine based on dynamic time warping, which is especially suited for embedded systems where the system resources are severely limited. We carried out some optimizations including speed optimization by programming time-critical functions in assembly language, and code size optimization and effective memory allocation. For the TMS320F2801 DSP which has 12Kbyte SRAM and 32Kbyte flash ROM, the recognizer developed can recognize 10 commands. For the TMS320F2808 DSP which has 36Kbyte SRAM and 128Kbyte flash ROM, it has additional capability of outputting the speech sound corresponding to the recognition result. The speech sounds for response, which are captured when the user trains commands, are encoded using ADPCM and saved on flash ROM. The single-chip recognizer needs few parts except for a DSP itself and an OP amp for amplifying microphone output and anti-aliasing. Therefore, this recognizer may play a similar role to dedicated speech recognition chips.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.12
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• pp.671-678
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• 2003

This paper proposes an expert system to generate automatically the test table of test system which can highly enhance the quality and productivity of product by inspecting quickly and accurately the defect device on the electronic circuit board tested. The expert system identifies accurately the tested components and the circuit patterns by tracing automatically the connectivity of circuit from electronic circuit database. And it generates automatically the test table to detect accurately the missing components, the misplaced components, and the wrong components for analog components such as resistance, coil, condenser, diode, and transistor, based on the experience knowledge of veteran expert. It is implemented in C computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique, the interface with the electronic circuit database and the hardware direct control. And, the validity of the builded expert system is proved by simulating for a typical electronic board model.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.52 no.5
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• pp.283-289
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• 2003

This paper proposes an expert system which can determine automatically the shunting routes corresponding to the given shunting works by considering totally the train operating environments in the station. The expert system proposes the multiple shunting routes with priority of selection based on heuristic search strategy. Accordingly, system operator can select a shunting route with the safety and efficiency among the those shunting routes. The expert system consists of a main inference engine and a sub inference engine. The main inference engine determines the shunting routes with selection priority using the segment routes obtained from the sub inference engine. The heuristic rules are extracted from operating knowledges of the veteran route operator and station topology. It is implemented in C computer language for the purpose of the implementation of the inference engine using the dynamic memory allocation technique. And, the validity of the builted expert system is proved by a test case for the model station.

• Journal of Korea Technology Innovation Society
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• v.8 no.3
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• pp.1027-1059
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• 2005

The purpose of this paper is to analyze the dynamic characteristics of innovation sources such as scientific knowledges, processing technologies and user's needs in advanced metals technology. The journal articles data of four advanced materials are analyzed; amorphous metals, superplastic materials, shape memory alloys and aluminum-lithium alloy. Some regularities are found from the analysis of the four materials. The innovation proceeds through close interactions among the innovation sources. As the innovation proceeds, the relative importance of each source changes: scientific knowledge initiates the innovation and becomes the most important source in the first phase, then the processing technologies increase importance in the second phase, and then scientific knowledge, again, becomes the leading factor of innovation. Scientific knowledge and processing technology take turns leading the innovation. The impacts of users' needs to the innovation increase more and more as innovation proceeds. The results of analysis imply to the policy makers that emphasis of policy, and therefore the allocation of sources for innovation, should vary along the phases in the life cycle of advanced metals technology.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.11
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• pp.572-580
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• 2007

Wireless sensor networks are sensing, computing and communication infrastructures that allow us to monitor, instrument, observe, and respond to phenomena in the harsh environment. Generally, the wireless sensor networks are composed of many deployed sensor nodes that were designed to be very cost-efficient in terms of production cost. For example, UC Berkeley's MICA motes have only 8-bit CPU, 4KB RAM, and 128KB FLASH memory space. Therefore, sensor operating systems that run on the sensor nodes should be able to operate efficiently in terms of the resource management. In this paper, we present a dynamic threads stack management scheme for space-constrained and multi-threaded sensor operating systems. In this scheme, the necessary stack space of each function is measured on compile-time. Then, the information is used to dynamically allocate and release each function's stack space on run-time. It was implemented in Nano-Qplus sensor operating system. Our experimental results show that the proposed scheme outperforms the existing fixed-size stack allocation mechanism.

• Journal of KIISE:Software and Applications
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• v.32 no.10
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• pp.1003-1012
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• 2005

The most significant difference of embedded systems from general purpose systems is that embedded systems are allowed to use only limited resources including battery and memory. Especially, the number of applications increases which deal with multimedia data. In those systems with high data computations, the delay of memory access is one of the major bottlenecks hurting the system performance. As a result, many researchers have investigated various techniques to reduce the memory access cost. Most programs generally have locality in memory references. Temporal locality of references means that a resource accessed at one point will be used again in the near future. Spatial locality of references is that likelihood of using a resource gets higher if resources near it were just accessed. The latest embedded processors usually adapt cache memory to exploit these two types of localities. Processors access faster cache memory than off-chip memory, reducing the latency. In this paper we will propose the enhanced dynamic allocation technique for structure-type data in order to eliminate unused memory space and to reduce both the cache miss rate and the application execution time. The proposed approach aggregates fields from multiple records dynamically allocated and consecutively remaps them on the memory space. Experiments on Olden benchmarks show $13.9\%$ L1 cache miss rate drop and $15.9\%$ L2 cache miss drop on average, compared to the previously proposed techniques. We also find execution time reduced by $10.9\%$ on average, compared to the previous work.

• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.289-293
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• 2000

We propose two new algorithms for parallelism-independent scheduling. The machine code generated from the compiler using these algorithms in its scheduling phase is parallelism-independent code, executable in minimum time regardless of the number of the processors in the parallel computer. Our new algorithms have the following phases: finding the minimum number of processors on which the program can be executed in minimal time, scheduling by an heuristic algorithm for this predefined number of processors, and serialization of the parallel schedule according to the earliest start time of the tasks. At run time tasks are taken from the serialized schedule and assigned to the processor which allows the earliest start time of the task. The order of the tasks decided at compile time is not changed at run time regardless of the number of the available processors which means there is no out-of-order issue and execution. The scheduling is done predominantly at compile time and dynamic scheduling is minimized and diminished to allocation of the tasks to the processors. We evaluate the proposed algorithms by comparing them in terms of schedule length to the CP/MISF algorithm. For performance evaluation we use both randomly generated DAGs (directed acyclic graphs) and DACs representing real applications. From practical point of view, the algorithms we propose can be successfully used for scheduling programs for in-order superscalar processors and shared memory multiprocessor systems. Superscalar processors with any number of functional units can execute the parallelism-independent code in minimum time without necessity for dynamic scheduling and out-of-order issue hardware. This means that the use of our algorithms will lead to reducing the complexity of the hardware of the processors and the run-time overhead related to the dynamic scheduling.

• Journal of Korea Society of Industrial Information Systems
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• v.8 no.4
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• pp.64-72
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• 2003

A Web crawler is an important Internet software technology used in a variety of Internet application software which includes search engines. As Internet continues to grow, implementations of high performance web crawlers are urgently demanded. In this paper, we study how to support dynamic scheduling for a multiprocess-based web crawler. For high peformance, web crawlers are usually based on multiprocess in their implementations. In these systems, crawl scheduling which manages the allocation of web pages to each process for loading is one of the important issues. In this paper, we identify issues which are important and challenging in the crawl scheduling. To address the issue, we propose a dynamic crawl scheduling framework and subsequently a system architecture for a web crawler with dynamic crawl scheduling support. And we analysed the behaviors of Web crawler. Based on the analysis result, we suggest the direction for the design of high performance Web crawler.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.7
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• pp.349-358
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• 2005

False sharing is a result of co-location of unrelated data in the same unit of memory coherency, and is one source of unnecessary overhead being of no help to keep the memory coherency in multiprocessor systems. Moreover. the damage caused by false sharing becomes large in proportion to the granularity of memory coherency. To reduce false sharing in a page-based DSM system, it is necessary to allocate unrelated data objects that have different access patterns into the separate shared pages. In this paper we propose call-site tracing-based shared memory allocator. shortly CSTallocator. CSTallocator expects that the data objects requested from the different call-sites may have different access patterns in the future. So CSTailocator places each data object requested from the different call-sites into the separate shared pages, and consequently data objects that have the same call-site are likely to get together into the same shared pages. We use execution-driven simulation of real parallel applications to evaluate the effectiveness of our CSTallocator. Our observations show that by using CSTallocator a considerable amount of false sharing misses can be additionally reduced in comparison with the existing techniques.