• Proceedings of the Korean Institute of Building Construction Conference
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• 2023.11a
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• pp.19-20
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• 2023

The pre-qualification system related to floor impact noise is considered ineffective, and thus, the introduction of a post-verification system is being prepared. This is because the performance, which was notarized in the qualification test due to various reasons, was not uniformly confirmed on building construction fields. Industry practitioners perceive that this is due to the influence of factors such as the flatness, levelness and/or thickness of the floor. However, it is very difficult to confirm such facts in a short period of time on the fields, and since the practical application of technology to measure and evaluate quantitatively and the establishment of a system are insufficient, it cannot be said to be a problem that can be brought to the surface. In fact, even when considering the conventional measurement of the dynamic modulus of elasticity, measurements are performed under controlled variables, such as placing a 200mm×200mm buffer material on a flat test-floor. However, in the fields, it is common to lay down larger productions(for example, 900mm×600mm) on the bare floor where significant variables are not controlled, and to construct finishing layers corresponding to the pre-qualified floor system without separately confirming the realization of the dynamic modulus of elasticity in the field conditions. In this study, spatial information of the bare floor on the field was measured and evaluated through a laser scanner. Technical methods for assessing the smoothness, flatness, and thickness of construction surfaces were reviewed, providing key insights for grading the quality of construction based on these criteria. Through further detailed and thorough investigations, it is expected that results suitable for practical application and systematization will be derived.

• Journal of Advanced Navigation Technology
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• v.19 no.5
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• pp.417-422
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• 2015

A service size of the IoT environment is determined by the number of sensors. The number of sensors increase means increases the amount of data generated by the IoT environment. There are studies to reliably operate a network for research and operational dynamic buffer for data when network congestion control congestion in the network environment. There are also studies of the stream data that has been processed in the connectionless network environment. In this study, we propose a sensor gateway for processing big data of the IoT environment. For this, review the RESTful for designing a sensor middleware, and apply the double-buffer algorithm to process the stream data efficiently. Finally, it generates a big data traffic using the MJpeg stream that is based on the HTTP protocol over TCP to evaluate the proposed system, with open source media player VLC using the image received and compare the throughput performance.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.11
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• pp.24-35
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• 2012

In this paper, we propose a dynamic lane control scheme with a traffic predictor module and a rate controller for reconciling with commercial optical PHY modules in energy efficient optical Ethernet systems. The commercial high speed optical Ethernet system capable of 40/100Gbps employs 4 or 10 multiple optical transceivers over WDM or multiple optical links. Each of the transceivers is always turned on even if the link is idle. To save energy, we propose the dynamic lane control scheme. It allows that several links may be entirely turned off in a low traffic load and frames are handled on the remaining active links. To preserve the byte order even if the number of active links may be changed, we propose a rate controller to be sat on the reconciliation sublayer. The main role of the controller is to insert null byte streams into the xGMII of inactive lanes. For the PHY module, the null input streams corresponding to inactive lanes will be disregarded on inactive PMDs. It is very handy to implement the rate controller module with MAC in FPGA without any modification of commercial PHYs. It is very crucial to determine the number of active links based on the fluctuated traffic load, we provide a simple traffic predictor based on both the current transmission buffer size and the past one with different weighting factors for adapting to the traffic load fluctuation. Using the OMNET++ simulation framework, we provide several performance results in terms of the energy consumption.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.1
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• pp.15-24
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• 2012

In this paper, we suggest the dynamic-response-free SMPS using a new high-resolution DPWM generator based on switched-capacitor delay technique. In the proposed system, duty ratio of DPWM is controlled by voltage slope of an internal capacitor using switched-capacitor delay technique. In the proposed circuit, it is possible to track output voltage by controlling current of the internal capacitor of the DPWM generator through comparison between the feedback voltage and the reference voltage. Therefore the proposed circuit is not restricted by the dynamic-response characteristic which is a problem in the existing SMPS using the closed-loop control method. In addition, it has great advantage that ringing phenomenon due to overshoot/undershoot does not appear on output voltage. The proposed circuit can operate at switching frequencies of 1MHz~10MHz using internal operating frequency of 100 MHz. The maximum current of the core circuit is 2.7 mA and the total current of the entire circuit including output buffer is 15 mA at the switching frequency of 10 MHz. The proposed circuit has DPWM duty ratio resolution of 0.125 %. It can accommodate load current up to 1 A. The maximum ripple of output voltage is 8 mV. To verify operation of the proposed circuit, we carried out simulation with Dongbu Hitek BCD $0.35{\mu}m$ technology parameter.

• The KIPS Transactions:PartC
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• v.14C no.1 s.111
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• pp.81-86
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• 2007

New multimedia services over the cellular/WLAN overlay networks require different Quality of Service (QoS). Therefore, efficient network management system is necessary in order to provide QoS sensitive multimedia services while enhancing network performance. In this paper, we propose a new online network management scheme that implements bandwidth reservation, congestion and transmission control strategies. Our online approach to network management exhibits dynamic adaptability, flexibility, and responsiveness to the current traffic conditions in multimedia overlay networks. Simulation results indicate the superior performance of our proposed scheme to strike the appropriate performance balance between contradictory QoS requirements under widely varying diverse traffic loads.

• Journal of the Korea Society for Simulation
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• v.9 no.4
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• pp.51-58
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• 2000

The control of the data retention time is a main issue for realizing future high density dynamic random access memory. The novel junction process scheme in sub-micron DRAM cell with STI(Shallow Trench Isolation) has been investigated to improve the tail component in the retention time distribution which is of great importance in DRAM characteristics. In this' paper, we propose the new implantation scheme by gate-related ion beam shadowing effect and buffer-enhanced ${\Delta}Rp$ (projected standard deviation) increase using buffered N-implantation with tilt and 4X(4 times)-rotation that is designed on the basis of the local-field-enhancement model of the tail component. We report an excellent tail improvement of the retention time distribution attributed to the reduction of electric field across the cell junction due to the redistribution of N-concentration which is Intentionally caused by ion Beam Shadowing and Buffering Effect using tilt implantation with 4X-rotation. And also, we suggest the least requirements for adoption of this new implantation scheme and the method to optimize the key parameters such as tilt angle, rotation number, Rp compensation and Nd/Na ratio. We used MEDICI Simulator to confirm the junction device characteristics. And measured the refresh time using the ADVAN Probe tester.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.1
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• pp.36-44
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• 2000

In this paper, we describe the developing of a tool which supports both multimedia presentation with user's participation through a high speed network and authoring of various media using a single authoring tool. To support real-time synchronous multimedia presentation, we adopt dynamic synchronization method and adaptive transmission algorithm for synchronizing data transfer rate between sender and receiver using buffer management algorithm based on QoS parameters. And we also allow user's participation in the presentation using TRSG(Temporal Relationship Specification Graph) model. Finally, the proposed tool supports the minimal level of QoS and its continuous play-out using event auditing threads which control the current state of a multimedia presentation continuously by monitoring of negative factors effecting on QoS, and synchronization.

• Journal of information and communication convergence engineering
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• v.20 no.2
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• pp.137-142
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• 2022

Monolithic three-dimensional (M3D) logics such as M3D-NAND, M3D-NOR, M3D-buffer, M3D 2×1 multiplexer, and M3D D flip-flop, consisting of modularized M3D inverters (M3D-INVs), have been proposed. In the previous M3D logic, each M3D logic had to be designed separately for a standard cell library. The proposed M3D logic is designed by placing modularized M3D-INVs and connecting interconnects such as metal lines or monolithic inter-tier-vias between M3D-INVs. The electrical characteristics of the previous and proposed M3D logics were simulated using the technology computer-aided design and Simulation Program with Integrated Circuit Emphasis with the extracted parameters of the previously developed LETI-UTSOI MOSFET model for n- and p-type MOSFETs and the extracted external capacitances. The area, propagation delay, falling/rising times, and dynamic power consumption of the proposed M3D logic are lower than those of previous versions. Despite the larger space and lower performance of the proposed M3D logic in comparison to the previous versions, it can be easily designed with a single modularized M3D-INV and without having to design all layouts of the logic gates separately.

• The KIPS Transactions:PartC
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• v.12C no.5 s.101
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• pp.695-700
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• 2005

To provide the fair rate and achieve the fair bandwidth allocation, many per-flow scheduling algorithms have been proposed such as fair queueing algorithm for congestion control. But these algorithms need to maintain the state, manage buffer and schedule packets on a per-flow basis; the complexity of these functions may prevent them from being cost-effectively implemented. In this paper, therefore, to acquire cost-effectively for implementation, we propose a CS-FNE(Core Stateless FNE) algorithm that is based on FM(Flow Number Estimation), and evaluated CS-FNE scheme together with CSFQ(Core Stateless Fair Queueing), FRED(Fair Random Early Detection), RED(Random Early Detection), and DRR(Dynamic Round Robin) in several different configurations and traffic sources. Through the simulation results, we showed that CS-FNE algorithm can allocate fair bandwidth approximately than other algorithms, and CS-FNE is simpler than many per-flow basis queueing mechanisms and it can be easily implemented.

• The KIPS Transactions:PartC
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• v.8C no.6
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• pp.805-814
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• 2001

In this paper, we propose a new scheduling algorithm that guarantees the delay property of real-time traffic, not considered in previous DWRR(Dynamic Weighted Round Robin) algorithm and also transmits non-real-time traffic efficiently. The proposed scheduling algorithm is a variation of DWRR algorithm to guarantee the delay property of real-time traffic by adding cell transmission method based on delay priority. It also uses the threshold to prevent the cell loss of non-real-time traffic due to cell transmission method based on delay priority. Proposed scheduling algorithm may increase some complexity over conventional DWRR scheme because of cell transmission method based on delay priority. However, the consideration of delay priority can minimize cell delay and require less size of temporary buffer. Also, the results of our performance study shows that the proposed scheduling algorithm has better performance than conventional DWRR scheme due to reliable ABR service and congestion avoidance capacity.