• Journal of Power Electronics
• /
• v.11 no.3
• /
• pp.271-278
• /
• 2011

This paper presents a LLC resonant controller IC for secondary side control without external active devices to achieve low profile and low cost LED back light units. A gate driving transformer is adopted to isolate the primary side and the secondary side instead of an opto-coupler. A new integrated dimming circuitry is proposed to improve the dynamic current control characteristic and the current density of a LED for the brightness modulation of a large screen LCD. A dual-slope clock generator is proposed to overcome the frequency error due to the under shoot in conventional approaches. This chip is fabricated using 0.35 ${\mu}m$ BCD technology and the die size is $2{\times}2\;mm^2$. The frequency range of the clock generator is from 50 kHz to 500 kHz and the range of the dead time is from 50 ns to 2.2 ${\mu}s$. The efficiency of the LED driving circuit is 97 % and the current consumption is 40 mA for a 100 kHz operation frequency from a 15 V supply voltage.

• Journal of the Korean Society of Industry Convergence
• /
• v.20 no.2
• /
• pp.115-124
• /
• 2017

This paper aims to develop an SMPS topology for handling a high range of input voltages based on a DC-DC flyback converter circuit. For this purpose, 2 capacitors of the same specifications were serially connected on the input terminal side, with a flyback converter of the same circuit configuration serially connected to each of them, so as to achieve high input voltage and an effect of dividing input voltage. The serially connected flyback converters have the transformer turn ratio of 1:1, so that each coil is used for the winding of a single transformer, which is a characteristic of doubly-fed configuration and enables the correction of input capacitor voltage imbalance. In addition, a pulse transformer was designed and fabricated in a way that can achieve the isolation and noise robustness of the PWM output signal of the PWM controller that applies gate voltage to individual flyback converter switches. PSIM simulation was carried out to verify such a structure and confirm its feasibility, and a 100W class stack was fabricated and used to verify the feasibility of the proposed high voltage SMPS topology.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2019.05a
• /
• pp.254-256
• /
• 2019

소수체 GF(p)와 이진체 $GF(2^m)$ 상의 다중 타원곡선을 지원하는 듀얼 필드 ECC (DF-ECC) 프로세서를 설계하였다. DF-ECC 프로세서의 저면적 설와 다양한 타원곡선의 지원이 가능하도록 워드 기반 몽고메리 곱셈 알고리듬을 적용한 유한체 곱셈기를 저면적으로 설계하였으며, 페르마의 소정리(Fermat's little theorem)를 유한체 곱셈기에 적용하여 유한체 나눗셈을 구현하였다. 설계된 DF-ECC 프로세서는 스칼라 곱셈과 점 연산, 그리고 모듈러 연산 기능을 가져 다양한 공개키 암호 프로토콜에 응용이 가능하며, 유한체 및 모듈러 연산에 적용되는 파라미터를 내부 연산으로 생성하여 다양한 표준의 타원곡선을 지원하도록 하였다. 설계된 DF-ECC는 FPGA 구현을 하드웨어 동작을 검증하였으며, 0.18-um CMOS 셀 라이브러리로 합성한 결과 22,262 GEs (gate equivalences)와 11 kbit RAM으로 구현되었으며, 최대 100 MHz의 동작 주파수를 갖는다. 설계된 DF-ECC 프로세서의 연산성능은 B-163 Koblitz 타원곡선의 경우 스칼라 곱셈 연산에 885,044 클록 사이클이 소요되며, B-571 슈도랜덤 타원곡선의 스칼라 곱셈에는 25,040,625 사이클이 소요된다.

• Progress in Medical Physics
• /
• v.20 no.4
• /
• pp.216-224
• /
• 2009

$^{131}I$ is a radiological isotope being used widely for treatment of cancer as emitting gamma-ray and it is also applied to estimate the function of thyroid for its accumulation in thyroid. However, $^{131}I$ is more difficult to quantitate comapred to $^{99m}Tc$, because $^{131}I$ has multiple energy gamma-ray emissions compared to $^{99m}Tc$ which is a mono energetic gamma-ray source. Especially, scattered ray and septal penetration resulted by high energy gamma ray have a bad influence upon nuclear medicine image. The purpose of this study was to estimate scatter components depending on the different source locations within a phantom using Monte Carlo simulation (GATE). The simulation results were validated by comparing with the results of real experiments. Dual-head gamma camera (ECAM, Chicago, Illinois Siemens) with high energy, general-purpose, and parallel hole collimators (hole radius: 0.17 cm, septal thickness: 0.2 cm, length: 5.08 cm) was used in this experiment. The NaI crystal is $44.5{\times}59.1\;cm$ in height and width and 0.95 cm in thickness. The diameter and height of PMMA phantom were 16 cm and 15 cm, respectively. The images were acquired at 5 different locations of $^{131}I$ point source within the phantom and the images of $^{99m}Tc$ were also acquired for comparison purpose with low energy source. The simulation results indicated that the scattering was influenced by the location of source within a phantom. The scattering effects showed the same tendency in both simulation and actual experiment, and the results showed that the simulation was very adequate for further studies. The results supported that the simulation techniques may be used to generalize the scattering effects as a function of a point source location within a phantom.

• The Korean Journal of Nuclear Medicine
• /
• v.38 no.5
• /
• pp.338-343
• /
• 2004

Purpose: The purpose of this study was to develop a small animal PET using dual layer phoswich detector to minimize parallax error that degrades spatial resolution at the outer part of field-of-view (FOV). Materials and Methods: A simulation tool GATE (Geant4 Application for Tomographic Emission) was used to derive optimal parameters of small PET, and PET was developed employing the parameters. Lutetium Oxyorthosilicate (LSO) and Lutetium-Yttrium Aluminate-Perovskite(LuYAP) was used to construct dual layer phoswitch crystal. $8{\times}8$ arrays of LSO and LuYAP pixels, $2mm{\times}2mm{\times}8mm$ in size, were coupled to a 64-channel position sensitive photomultiplier tube. The system consisted of 16 detector modules arranged to one ring configuration (ring inner diameter 10 cm, FOV of 8 cm). The data from phoswich detector modules were fed into an ADC board in the data acquisition and preprocessing PC via sockets, decoder block, FPGA board, and bus board. These were linked to the master PC that stored the events data on hard disk. Results: In a preliminary test of the system, reconstructed images were obtained by using a pair of detectors and sensitivity and spatial resolution were measured. Spatial resolution was 2.3 mm FWHM and sensitivity was 10.9 $cps/{\mu}Ci$ at the center of FOV. Conclusion: The radioactivity distribution patterns were accurately represented in sinograms and images obtained by PET with a pair of detectors. These preliminary results indicate that it is promising to develop a high performance small animal PET.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.4
• /
• pp.795-803
• /
• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.4A
• /
• pp.387-393
• /
• 2008

In this paper, we present an SDR (Software Defined Radio) handset modem platform which supports communication systems such as HSDPA (High Speed Downlink Packet Access), and WiBro (Wireless Broadband Portable Internet). The proposed SDR platform employs DSPs (Digital Signal Processors), FPGAs (Field Programmable Gate Arrays), and microprocessors in such a way that the various communication functions like HSDPA and WiBro can be programmed and downloaded to the hardware platform. The proposed SDR platform can be used for functional verification of the physical layers of the mobile handset system in the mobile communication network. We first demonstrate the receiving structure of the physical layer of the HSDPA and WiBro system. Then, the hardware implementation of the proposed SDR platform is shown with functions and optimized signal flows required at each mode. Finally, the link performance of each mode operating on the proposed SDR platform is presented through the internal loopback tests with the test vectors. The experimental performance has been compared with the computer simulation results.

• Korean Journal of Optics and Photonics
• /
• v.24 no.5
• /
• pp.262-270
• /
• 2013

In this paper, we propose a modified optical CBC(Cipher Block Chaining) encryption method using optical XOR logic operations. The proposed method is optically implemented by using dual encoding and a free-space interconnected optical logic gate technique in order to process XOR operations in parallel. Also, we suggest a CBC encryption/decryption optical module which can be fabricated with simple optical architecture. The proposed method makes it possible to encrypt and decrypt vast two-dimensional data very quickly due to the fast optical parallel processing property, and provides more security strength than the conventional electronic CBC algorithm because of the longer security key with the two-dimensional array. Computer simulations show that the proposed method is very effective in CBC encryption processing and can be applied to even ECB(Electronic Code Book) mode and CFB(Cipher Feedback Block) mode.

• Journal of the Korean Institute of Landscape Architecture International Edition
• /
• no.1
• /
• pp.89-101
• /
• 2001

The purpose of this study ins to verify the characteristic location of Byungyoung Castle, physical type, inside spatial organization, and the scheme of Byungyoung Castle. The study utilizes historic literature, ancient maps related to Byungyoung Castle, topographical and cadastral maps which were published under the rule of Japanese Imperialism Castle, topographical and cadastral maps which were published under the rule of Japanese Imperialism and the topographical maps which were made recently by National Geographic Institute with various scales. The methodology of the study is to interpret the contents from the historic literature on the site map. The methodology of the study is to interpret the contents from the historic literature on the site map. The result of the study is as follows; Byungyoung Castle does duty as a defensive base for the entire country and has a specific character of location that has the dual function of a mountain fortress for national defense and of a village fortress for the town. Byungyoung Castle has four gates on four sides and has a oval shape very close to a circular form. The road construction inside the castle is composed basically of a cross shape. Byungyoung is located in the northwest area of this major road system. The private houses that lie along the north-south road are build up at the core area of the lower level and the town market built up around the south gate becomes the heart of life for the people. Schematically, it has the same pattern as regular village fortress, in that the houses for the guests and the houses for the public office are arranged to the east and the west. It is considered that there is certain functional parallel between Byungyoug Castle and Ulsan castle because there are no facilities for sacrificial rites no institutional budding.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.23 no.8
• /
• pp.966-974
• /
• 2019

In this study, we propose a CMOS power amplifier (PA) using a bypass technique to enhance the efficiency in the low-power region. For the bypass structure, the common-gate (CG) transistor of the cascode structure of the driver stage is divided in two parallel branches. One of the CG transistors is designed to drive the power stage for high-power mode. The other CG transistor is designed to bypass the power stage for low-power mode. Owing to a turning-off of the power stage, the power consumption is decreased in low-power mode. The measured maximum output power is 20.35 dBm with a power added efficiency of 12.10%. At a measured output power of 11.52 dBm, the PAE is improved from 1.90% to 7.00% by bypassing the power stage. Based on the measurement results, we verified the functionality of the proposed bypass structure.