• Korean Journal of Materials Research
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• v.12 no.3
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• pp.200-204
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• 2002

We fabricated TMR devices which have double oxidized tunnel barrier using plasma oxidation method to form homogeneously oxidized AlO tunnel barrier. We sputtered 10 $\AA$-bottom Al layer and oxidized it by varying oxidation time for 5, 10, 20 sec. Subsequent sputtering of 13 $\AA$ - Al was performed and the matallic layer was oxidized for 120 sec. The electrical resistance changed from 700$\Omega$ to 2700$\Omega$ with increase of oxidation time, while variation of MR ratio was little spreading 27~31% which is larger than that of TMR device of ordinary single tunnel barrier. We calculated effective barrier height and width by measuring I-V curves, from which we found the barrier height was 1.3~1.5 eV, sufficient for tunnel barrier, and the barrier width(<16.2 $\AA$) was smaller than that of directly measured value by the tunneling electron microscopy. Our results may be caused by insufficient oxidation of Al precursor into $Al_2O_3$. However, double oxidized tunnel barriers were superior to conventional single tunnel barrier in uniformity and density. We found that the external magnetic field to switch spin direction of ferromagnetic layer of pinned layer breaking ferro-antiferro exchange coupling was increased as bottom layer oxidation time increased. Our results imply that we were able to improve MR ratio and tune switching field by employing double oxidized tunnel barrier process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.652-655
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• 2001

In this paper, I have studied minimization of the kerf-width and surface burning which are occurred after the singulation process of multi layer $\mu$-BGA( thickness 1.1 mm, 0.9 mm) with a pulsed Nd:YAG( = 532 nm, repetition rate = 10 Hz) laser. The thermal energy of a pulsed Nd:YAG laser is used to cut the copper layer. I have studied are minimization of the surface burning and kerf-width using a photo resist, $N_2$blowing and polyester double sided tape as a cutting parameter. The $N_2$blowing reduces a laser energy loss by debris and suppresses a surface carbonization. Also, I have studied characters of cutting with a choice of side of laser beam incidence. The SEM(Scanning Electron Microscope), non-contact 3D inspector and high-resolution microscope are used to measure kerf width and surface state. The optimum value of 1.1 mm $\mu$-BGA singulation is 524 $\mu$m that is reduced kerf width of 60 % with $N_2$blowing. And I obtained reduction of carbonization of 68 % with a polyester double side tape in 0.9 mm $\mu$-BGA. I used laser intensity of 1.91$\times$10$^{6}$ / $\textrm{cm}^2$ in this study.

• Journal of the Korean Society of Clothing and Textiles
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• v.44 no.3
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• pp.427-440
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• 2020

This study developed a vest prototype capable of monitoring body temperature using textile electrodes to prevent the sudden death of babies as well as to determine the quality of developed products by evaluating usability with commercial products. Based on the results of the 7th Size Korea Project, a basic pattern for a vest prototype was drafted by applying the average size of two-year-old Korean babies. Two prototypes were the detachable (VEST I) and integrated textile electrodes vest type (VEST II), which followed the same design. The materials were 100% cotton single jersey (SJ) and double jersey (DJ). Six experts evaluated the usability of the developed vests (VEST I & VEST II) and commercial product (VEST M). The single-layer woven textile electrode appeared to have a slightly higher conductivity than the double-layer one. There was no statistical difference in the body temperature sensing function between VEST I and VEST II. Finally, the superiority of the VEST I was verified through a comparison with commercial products (VEST M). The usability test suggested that a wearable smart clothing system of the integrated conductive textile could be further commercialized for bio-monitor applications in Ubiquitous-health care.

• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.119-120
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• 2006

The impedance spectroscopy is one of the effective ways to understand the electrical properties of organic light emitting diodes. The frequency-dependant properties of small molecule based OLEDs have been studied. The equivalent circuit of single-layer device is composed of contact resistance ($R_c$), bulk resistance ($R_p$) and bulk capacitance ($C_p$). The equivalent circuit of double layer device is composed of two parallel circuits connected in series, each of which is a parallel resistor and a capacitor. We have fabricated a double layer device indium-rio-oxide (ITO, anode), N,NV -diphenyl- N,NV -bis(3-methylphenyI)-1,1V -diphenyl-4,4V-diamine (TPD, hole-transporting layer), tris-(8-hydroxyquinoline) aluminum (Alq3, emitting layer), and aluminum (AI, cathode) and two single layer devices ([TO/ Alq3/ AI, ITO/TPD/AI).

• Composites Research
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• v.31 no.5
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• pp.177-185
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• 2018

Fiber metal laminate (FML) is a type of hybrid composites which consist of metallic and fiber-reinforced plastic sheets. As the FML has a drawback of the delamination that is a failure of the interfacial adhesive layer, the nominal stresses and the energy release rates should be determined to identify the delamination behavior. However, it is difficult to derive the nominal stresses and the energy release rates since the operating temperature of the equipment is restricted. For this reason, the objective of this paper is to predict the mode-I nominal stress and the mode-I energy release rate of the adhesive layer using the inverse analysis based on the Levenberg-Marquardt method. First, the mode-I nominal stress was assumed as the tensile strength of the adhesive layer, and the mode-I energy release rate was obtained from the double cantilever beam test. Next, the finite element method was applied to predict the mode-I delamination behavior. Finally, the mode-I nominal stress and the mode-I energy release rate were predicted by the inverse analysis. In addition, the convergence of the parameters was validated by trying to input two cases of the initial parameters. Consequently, it is noted that the inverse analysis can predict the mode-I delamination behavior, and the two input parameters were converged to similar values.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.7
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• pp.63-68
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• 1994

The Curie point annealing effects on electrophysical phenomena at the magnetized strontium ferrite(SrO$\cdot$ 6$Fe_{2}O_{3}$) ceramics electrode/10$^{-3}$M KC1 aqueous electrolyte interfaces have been studied using cyclic voltammetric, normal pulse voltammetric, chronocoulometric, and electrochemical impedance techiques. After the Curie point annealing the magnetic flux densities of the speciment was decreased from 900-1100 gauss to 1-2 gauss, i.e. demagnetized. The real component of interfacial impedance was decreased from 7280-7320 ohm to 790-830 ohm. The adsorption and the charge on the electrical double layer was increased from 0 $\mu$C to -58 $\mu$C. The Curie point annealing and the related electrical double layer effect can influence not only the electrophysical properties of the strontium ferrite ceramics electrode itself but also the electrochemical phenomena at the electrode interface. This experimental results suggest that the Curie point annealing and the related electrical double layer effect can be applied to electrochemical magnetic sensors.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.39-39
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• 2009

We fabricated p-channel TFTs based on poly Silicon. The 35nm thickness silicon dioxide layer structure got higher $I_{on}/I_{off}$ ratio, field-effect Mobility and output current than 10nm thickness. And 35nm layer showed low leakage current and threshold voltage. So, 35nm thickness silicon dioxide layer TFTs are faster reaction speed and lower power consumption than 10nm thickness.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.2
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• pp.127-138
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• 2013

The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of $VIP_2$ and $VIP_3$. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.1625-1630
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• 2004

An experimental study was carried out to investigate influence of flow conditions on a boundary layer to the near-wake of a flat plate. The flow condition in the vicinity of trailing edge that is influenced by upstream condition history is an essential factor that determines the physical characteristics of a near-wake. Various tripping wires were used to change boundary layer flow condition of upstream at the freestream velocity of 6.0 m/sec. Measurements of the boundary layer and near-wake according to the change of upstream conditions were conducted by using both I-probe(55P14 for boundary layer) and X-probe(55P61 for wake). Normalized velocity profiles of the boundary layer were shown the flow types such as laminar boundary layer, transition, and turbulent boundary layer at 0.95C from the leading edge. The velocity and turbulence intensity profiles of the near-wake for the case of laminar boundary layer at the flat plate surface exhibited a defect and a double peak showing perfect symmetry, respectively.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.5
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• pp.737-748
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• 1995

In this paper, we studyed the variables in the design of multichip memory modules with 4M$\times$1bit DRAM chips to construct high capacity and high speed memory modules. The configuration of the module was 8 bit, 16 bit, and 32 bit DRAM modules with employing 0.6 W, 70 nsec 4M$\times$1 bit DRAM chips. We optimized routing area and wiring density by performing the routing experiment with the variables of the chip allocation, module I/O terminal, the number of wiring, and the number of mounting side of the chips. The multichip module was designed to be able to accept MCM-L techiques and low cost PCB materials. The module routing experiment showed that it was an efficient way to align chip I/O terminals and module I/O terminals in parallel when mounting bare chips, and in perpendicular when mounting packaged chips, to set module I/O terminals in two sides, to use double sided substrates, and to allocate chips in a row. The efficient number of wiring layer was 4 layers when designing single sided bare chip mounting modules and 6 layers when constructing double sided bare chip mounting modules whereas the number of wiring layer was 3 layers when using single sided packaged chip mounting substrates and 5 layers when constructing double sided packaged chip mounting substrates. The most efficient configuration was to mount bare chips on doubled substrates and also to increase the number of mounting chips. The fabrication of memory multichip module showed that the modules with bare chips can be reduced to a half in volume and one third in weight comparing to the module with packaged chips. The signal propagation delay time on module substrate was reduced to 0.5-1 nsec.