• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.12
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• pp.2615-2621
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• 2010

The multi-band six-port phase correlator using metamaterial was designed and fabricated in this paper. The lumped metamaterial structure that can process the dual-band receiving signal was analyzed. Based on the analyzed results, the small-sized metamatrial six-port phase correlator for multi-band direct conversion method was proposed and fabricated. Also, the resistive power divider and $90^{\circ}$ hybrid coupler that comprises the six-port phase correlator were implemented based on the scattering parameters of metamatrial six-port phase correlator. The measured results of the proposed six-port phase correlator show the good agreement with simulation results. The performance of the six-port phase correlator shows the reflection loss below -20 dB in the dual-band. Also, the proposed six-port phase correlator got a good transmission characteristic within 1 dB gain difference and ${\pm}4.1^{\circ}$ phase imbalance, respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.75-76
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• 2016

Even if ICS(Interference Cancellation System) repeater is used in wireless communication system, it has the disadvantage that it must have enough distance between Donor and Service antenna to be isolated. In this paper, new ICS repeater integrated antenna with high insolation characteristics is designed. The proposed antenna is fabricated for 800MHz and measured. Bandwidth and gain are optimized by changing the stub lengths near main patch and power divider, and also by changing the size of parasitic patch. This antenna has a return loss less than -13 dB, a gain over 3 dBi, and an isolation between the donor and the server antennas less than -56 dB from 824~894 MHz for CDMA mobile communication. Therefore, the proposed antenna structure can be applied to eliminate the shadow area and to expand the coverage area for any other wireless communication bands.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.8
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• pp.598-609
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• 2003

This paper describes a CMOS IF PLL frequency synthesizer. The designed frequency synthesizer can be programmed to operate at various intermediate frequencies using different external LC-tanks. The VCO with automatic amplitude control provides constant output power independent of the Q-factor of the external LC-tank. The designed frequency divider includes an 8/9 or 16/17 dual-modulus prescaler and can be programmed to operate at different frequencies by external serial data for various applications. The designed circuit is fabricated using a 0.35${\mu}{\textrm}{m}$ n-well CMOS process. Measurement results show that the phase noise is 114dBc/Hz@100kHz and the lock time is less than 300$mutextrm{s}$. It consumes 16mW from 3V supply. The die area is 730${\mu}{\textrm}{m}$$\times$950${\mu}{\textrm}{m}$.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.844-847
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• 2012

By using LHTL(Left-Handed Transmission Line) which is a form of a metamaterial and conventional RHTL (Right-Handed Transmission Line), we designed, fabricated and tested a broadband $90^{\circ}$ coupler which is a basic circuit for I-Q vector signal generation. Synthetic LHTL and RHTL were implemented with capacitors and inductors only, that the size is minimized. Also, by implementing a Wilkinson power divider which is required for the suggested circuit using a synthetic RHTL, the size of whole circuit is only $11mm{\times}12mm$. For the frequency range 0.8~1.25 GHz, the phase difference at the outputs maintained $90^{\circ}{\pm}5^{\circ}$ and thus, a broadband $90^{\circ}$ coupler could be made in a compact form. for the same frequency range, the insertion loss is less than 1.6 dB and return loss is more than 10.1 dB. To the best of our knowledge, this is the smallest and broadband $90^{\circ}$ coupler for the frequency range and if the circuit is made with MMIC(Monolithic Microwave Integrated Circuit) technology, the size will be reduced much further.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.3
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• pp.264-272
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• 2009

In this paper, a Ka-band 10 W power amplifier module is designed and fabricated using MIC(Microwave Integrated Circuit) module technology which combines multiple power MMIC(Monolithic Microwave Integrated Circuit) chips on a thin film substrate. Modified Wilkinson power dividers/combiners are used for millimeter wave modules and CBFGC-PW-Microstrip transitions are utilized for reducing connection loss and suppressing resonance in the high-gain and high-power modules. The power amplifier module consists of seven MMIC chips and operates in a pulsed mode. for the pulsed mode operation, a gate pulse control circuit supplying the control voltage pulses to MMIC chips is designed and applied. The fabricated power amplifier module shows a power gain of about 58 dB and a saturated output power of 39.6 dBm at a center frequency of the interested frequency band.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.5
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• pp.1071-1077
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• 2010

The six-port phase correlator using lumped elements was designed and fabricated in this paper, also the receiving performance of L-band direct conversion receiver using lumped six-port phase correlator element was analyzed. The proposed L-band lumped six-port phase correlator element was composed of a resistive power divider and the twist-wire coaxial cables. The proposed lumped six-port structure provides the small-sized configuration and wide-band characteristics. The performance of the L-band lumped direct conversion receiver structure was measured under the conditions of 1.69 GHz frequency for LO-CW signal and RF-QPSK signal, which are input signals for the lumped six-port phase correlator element. The direct conversion receiving structure using the proposed lumped six-port phase correlator element can recovered the good digital I/Q signal.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.8
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.134-141
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• 2007

This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.

• Journal of Sensor Science and Technology
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• v.7 no.4
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• pp.293-299
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• 1998

An objective of this study is to develop a voltage measuring device that uses a gas-filled switch (GS) on 22.9 kV-y extra-high voltage distribution lines. The voltage measuring device proposed in this paper is a kind of capacitive divider which consists of a detecting electrode attached outside of the bushing of GS, an impedance matching circuit, and a voltage buffer. It can be easily installed in an established GS without changing the structure. For the calibration and application investigations, the voltage measuring device was set up in the 25.8 kV 400 A GS, and a step pulse generator having 5 ns rise time is used. As a result, it was found that the frequency bandwidth of the voltage measuring device ranges from 1.35 Hz to about 13 MHz. The error of voltage dividing ratio which is evaluated by the commercial frequency voltage of 60 Hz was less than 0.2%. In addition, voltage dividing ratio in the commercial frequency voltage and in a non-oscillating impulse voltage were compared, and their deviation were less than 0.7%.

• Journal of Sensor Science and Technology
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• v.5 no.3
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• pp.9-16
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• 1996

This paper deals with the capacitive voltage divider which can measure a transient voltages generated by operating a high voltage impulse generator. The transient voltage measuring system using the capacitive electric field sensor consists of the planar-type electric field sensor having a fast response characteristic and the wide-bandwidth voltage follower, and the input impedance of which is extremely high, about $10^{12}{\Omega}$. In order to analyze the response characteristics to a step input, the newly developed calibration method is proposed, and the error of voltage dividing ratio associated with set-up condition is investigated. Also the optimal set-up condition that is to be maintained within the range of 0.5 % is taken. From the calibration experiment, the frequency bandwidth of the transient voltage measuring system whose response time to a step input is about 15.8 ns, is from 6.37 Hz to 27.3 MHz. Therefore it is possible to measure the commercial frequency voltages as well as the transient over voltages without signal distortions.