• Title/Summary/Keyword: discrete Hartley transform (DHT)

Search Result 4, Processing Time 0.009 seconds

Low Complexity Discrete Hartley Transform Precoded OFDM System over Frequency-Selective Fading Channel

  • Ouyang, Xing;Jin, Jiyu;Jin, Guiyue;Li, Peng
    • ETRI Journal
    • /
    • v.37 no.1
    • /
    • pp.32-42
    • /
    • 2015
  • Orthogonal frequency-division multiplexing (OFDM) suffers from spectral nulls of frequency-selective fading channels. Linear precoded (LP-) OFDM is an effective method that guarantees symbol detectability by spreading the frequency-domain symbols over the whole spectrum. This paper proposes a computationally efficient and low-cost implementation for discrete Hartley transform (DHT) precoded OFDM systems. Compared to conventional DHT-OFDM systems, at the transmitter, both the DHT and the inverse discrete Fourier transform are replaced by a one-level butterfly structure that involves only one addition per symbol to generate the time-domain DHT-OFDM signal. At the receiver, only the DHT is required to recover the distorted signal with a single-tap equalizer in contrast to both the DHT and the DFT in the conventional DHT-OFDM. Theoretical analysis of DHT-OFDM with linear equalizers is presented and confirmed by numerical simulation. It is shown that the proposed DHT-OFDM system achieves similar performance when compared to other LP-OFDMs but exhibits a lower implementation complexity and peak-to-average power ratio.

Parallel Processing Implementation of Discrete Hartley Transform using Systolic Array Processor Architecture (Systolic Array Processor Architecture를 이용한 Discrete Hartley Transform 의 병렬 처리 실행)

  • Kang, J.K.;Joo, C.H.;Choi, J.S.
    • Proceedings of the KIEE Conference
    • /
    • 1988.07a
    • /
    • pp.14-16
    • /
    • 1988
  • With the development of VLSI technology, research on special processors for high-speed processing is on the increase and studies are focused on designing VLSI-oriented processors for signal processing. This paper processes a one-dimensional systolic array for Discrete Hartley Transform implementation and also processes processing element which is well described for algorithm. The discrete Hartley Transform(DHT) is a real-valued transform closely related to the DFT of a real-valued sequence can be exploited to reduce both the storage and the computation requried to produce the transform of real-valued sequence to a real-valued spectrum while preserving some of the useful properties of the DFT is something preferred. Finally, the architecture of one-dimensional 8-point systolic array, the detailed diagram of PE, total time units concept on implementation this arrays, and modularity are described.

  • PDF

A unified systeolic array for computation of the 2D DCT/DST/DHT (2D DCT/DST/DHT 계산을 위한 단일화된 시스톨릭 어레이)

  • 반성범;박래홍
    • Journal of the Korean Institute of Telematics and Electronics B
    • /
    • v.33B no.2
    • /
    • pp.103-110
    • /
    • 1996
  • In this paper, we propose a unified systolic array for the computation of the 2D discrete cosine transform/discrete sine transform/discrete hartley transform (DCT/DST/DHT). The unified systeolic array for the 2D DCT/DST/DHT is a generalization of the unified systolic array for the 1D DCT/DST/DHT. In order to calculate the 2D transform, we compute 1D transforms along the row, transpose them, and obtain 1D transforms along the column. When we compare the proposed systolic array with the conventional method, our architecture exhibits a lot of advantages in terms of latency, throughput, and the number of PE's. The simulation results using very high speed integrated circuit hardware description language (VHDL), international standard language for hardware description, show the functional validity of the proposed architecture.

  • PDF

A Generalized Multicarrier Communication System - Part III: Dual Symbol Superposition Block Carrier Transmission with Frequency Domain Equalization

  • Imran Ali
    • International Journal of Computer Science & Network Security
    • /
    • v.24 no.9
    • /
    • pp.41-49
    • /
    • 2024
  • This paper proposes dual symbol superposition block carrier transmission with frequency domain equalization (DSS-FDE) system. This system is based upon χ-transform matrix, which is obtained by concatenation of discrete Hartley transform (DHT) matrix and discrete Fourier transform (DFT) matrices into single matrix that is remarkably sparse, so that, as it will be shown in this paper, it only has non-zero entries on its principal diagonal and one below the principle anti-diagonal, giving it shape of Latin alphabet χ. When multiplied with constellation mapped complex transmit vector, each entry of resultant vector is weighted superposition of only two entries of original vector, as opposed to all entries in conventional DFT based OFDM. Such a transmitter is close to single carrier block transmission with frequency domain equalization (SC-FDE), which is known to have no superposition. The DSS-FDE offers remarkable simplicity in transmitter design and yields great benefits in reduced complexity and low PAPR. At receiver-end, it offers the ability to harvest full diversity from multipath fading channel, full coding gain, with significant bit error rate (BER) improvement. These results will be demonstrated using both analytical expressions, as well as simulation results. As will be seen, this paper is Part III of three-paper series on alternative transforms for multicarrier communication (MC) systems.