• Journal of Institute of Control, Robotics and Systems
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• v.14 no.9
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• pp.939-947
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• 2008

The GPS tracking loop consists of three parts in general: discriminator, loop filter and DCO (Digitally Controlled Oscillator). The loop filter is the main part of the tracking loop designed to ensure a good tracking performance. Generally, the loop filter is designed using classical PI(Proportional Integral) control. Although the carrier Doppler and code Doppler are generated by the same relative movement between the satellite and the user, often, the loop filters for each tracking loop are designed separately and independently. Sometimes, they are used in a combined manner such as carrier aided code tracking, FLL assisted PLL, etc. For better GPS signal tracking, we need to design the FLL/PLL/DLL altogether optimally. The purpose of this paper is to design a GPS receiver tracking loop based on the Kalman filter in a combined manner. Also, the proposed GPS receiver tracking loop is compared with a conventional tracking loop in terms of the transfer function and the DCO input. This paper shows that conventional tracking loop is equal to the Kalman filter based tracking loop.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.8
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• pp.784-789
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• 2011

In this paper, a tunable integrated transmitter leakage canceller based on an autotransformer for ultra-high-frequency (UHF) RFID readers is presented. The proposed TX leakage canceller consists of an autotransformer, a digital tuning capacitor, a voltage controlled tuning resistor, and a compensating amplifier, and it is designed using 0.13 ${\mu}m$ 1-poly 6-metal RF CMOS process. The simulation results show that the proposed structure has over 55 dB rejection characteristic between a transmitter and a receiver and a 2.5 dB of the RX insertion loss. The TX leakage canceller can be digitally tuned from 825 MHz to 985 MHz with the tuning capacitor and it can be fully integrated.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2212-2220
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• 2016

Based on the conventional PID algorithm and the adaptive PID (AD-PID) algorithm, a separate sampling adaptive PID (SSA-PID) algorithm is proposed to improve the transient response of digitally controlled DC-DC converters. The SSA-PID algorithm, which can be divided into an oversampled adaptive P (AD-P) control and an adaptive ID (AD-ID) control, adopts a higher sampling frequency for AD-P control and a conventional sampling frequency for AD-ID control. In addition, it can also adaptively adjust the PID parameters (i.e. $K_p$, $K_i$ and $K_d$) based on the system state. Simulation results show that the proposed algorithm has better line transient and load transient responses than the conventional PID and AD-PID algorithms. Compared with the conventional PID and AD-PID algorithms, the experimental results based on a FPGA indicate that the recovery time of the SSA-PID algorithm is reduced by 80% and 67% separately, and that overshoot is decreased by 33% and 12% for a 700mA load step. Moreover, the SSA-PID algorithm can achieve zero overshoot during startup.

• Journal of Power Electronics
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• v.16 no.3
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• pp.823-831
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• 2016

A high-efficiency method is proposed to suppress magnetic core imbalance in phase-shifted full-bridge (PSFB) converters. Compared with conventional solutions, such as controlling peak current mode (PCM) or adding DC blocking capacitance, the proposed method has several advantages, such as lower power loss and smaller size, because the additional current sensor or blocking capacitor is removed. A time domain model of the secondary side is built to analyze the relationship between transformer core imbalance and cathode voltage of secondary side rectifiers. An approximate control algorithm is designed to achieve asymmetric phase control, which reduces the effects of imbalance. A 60 V/15 A prototype is built to verify the proposed method. Experimental results show that the numerical difference of primary side peak currents between two adjacent cycles is suppressed from 2 A to approximately 0 A. Meanwhile, compared with the PCM solution, the efficiency of the PSFB converter is slightly improved from 93% to 93.2%.

• Journal of Korean Academy of Oral and Maxillofacial Radiology
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• v.28 no.1
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• pp.17-26
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• 1998

The purpose of this study was to investigate whether a radiographic estimate of osseous fractal dimension is useful in the characterization of structural changes in bone. Ten specimens of bone were progressively decalcified in fresh 50 ml solutions of 0.1 N hydrochloric acid solution at cummulative timed periods of 5, 10, 20, 30, 60 and 90 minutes, and radiographed from 0 degree projection angle controlled by intraoral parelleling device. The test set of 70 radiographs was digitized and digitally filtered to reduce film -grain noise. I performed one-dimensional variance and fractal analysis of bony profiles or scan lines. Correlation analysis quantified the relationship between variance and fractal dimension. The obtained results were as follow. 1. After the first stage of decalcification variance and fractal dimension of scan line pixel intensities generally decreased with a range of 57.94 to 12.64 and 1.59 to 1.36. 2. Correlation coefficient(r) relating variances to fractal dimensions was consistantly excellent(range r=0.90 to 0.98). 3. Variance and fractal dimension were much alike in ability to discriminate, at leat on a group basis, between control and decalcified specimens.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.19 no.8
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• pp.122-130
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• 2005

For silent operation, Roll-Screen has been designed by using piezolelectric ultrasonic motor. To drive the ultrasonic motor, a digitally controlled drive system has been designed by using PLD. And to measure the position and velocity of Roll-Screen, encoder with 36 pulse/revolution is used. This paper proposed a new method for a precise velocity control of ultrasonic motor, in spite of using low-level encoder. The proposed method use a non-fixed sampling time and compensate the initial nonlinear characteristics of ultrasonic motors.

• Asian Journal of Innovation and Policy
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• v.8 no.1
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• pp.1-30
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• 2019

The advent of digitalisation has transformed economies into more integrated, but increasingly complex systems. This new trend has brought dynamic changes in the manufacturing sector through advanced ICT infrastructure, smart factories, digitally-controlled logistics, and skilled ICT-labour. The impacts of the digital economy on manufacturing could be best illustrated through "Industry 4.0." With this wave of technological advancement, countries aim to establish an industrial ecosystem where every manufacturing process and function is connected and interacts through digital networks. Industry 4.0 presents opportunities for Emerging Asia, as the region has emerged as a fast-growing manufacturing hub and particularly a production base for ICT goods. However, growing production capacity, increased exports, and increases in FDI in the field of ICT goods manufacturing have so far contributed little to the development and diffusion of ICT. A huge gap exists in the ICT uptake amongst countries and between small and large firms. This paper highlights the level of Industry 4.0 readiness of Emerging Asia and key factors that determine its enhancement.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.70-77
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• 2013

We suggest a low area and high efficiency switched-mode power supply (SMPS) with a pulse width modulation (PWM) generator based on a pseudo relaxation-oscillating technique. In the proposed circuit, the PWM duty ratio is determined by the voltage slope control of an internal capacitor according to amount of charging current in a PWM generator. Compared to conventional SMPSs, the proposed control method consists of a simple structure without the filter circuits needed for an analog-controlled SMPS or the digital compensator used by a digitally-controlled SMPS. The proposed circuit is able to operate at switching frequency of 1MHz~10MHz, as this frequency can be controlled from the selection of one of the internal capacitors in a PWM generator. The maximum current of the core circuit is 2.7 mA, and the total current of the entire circuit including output buffer driver is 15 mA at 10 MHz switching frequency. The proposed SMPS has a simulated maximum ripple voltage of 7mV. In this paper, to verify the operation of the proposed circuit, we performed simulation using Dongbu Hitek BCD $0.35{\mu}m$ technology and measured the proposed circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.17-22
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• 2006

CMOS LC VCO with fast response adaptive frequency calibration (AFC) technique for IEEE 802.11a/b/g WLANs is designed in 1.8V $0.18{\mu}m$ CMOS process. The possible operation is verified for 5.8GHz band, 5.2GHz band, and 2.4GHz band using the switchable L-C resonators. To linearize its frequency-voltage gain (Kvco), optimized multiple MOS varactor biasing tecknique is used. In order to operate in each band frequency range with reduced VCO gain, 4-bit digitally controlled switched- capacitor bank is used and a wide-range digital logic quadricorrelator (WDLQ) is implemented for fast frequency detector.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.10
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• pp.7-13
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• 2010

A compact phase interpolator (PI) based spread spectrum clock generator (SSCG) for electromagnetic interference (EMI) reduction is presented. The proposed SSCG utilizes a digitally controlled phase interpolation technique to achieve triangular frequency modulation with less design complexity and small power and area overhead. The novel SSCG can generate the system clock with a programmable center-spread spectrum range of up to +/- 2 % at 200 MHz, while maintaining the clock duty cycle ratio without distortions. The PI-based SSCG has been designed and evaluated in 0.18-um 1.8-V CMOS technology, which consumes about 5.0 mW at 200MHz and occupies a chip size of $0.092mm^2$ including a DLL.