• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.115-122
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• 1997

In this paper, on-chp atomatic tuning circuit, using proposed integration level approximation technique, is designed to tuning of the variation of RC time-constant due to aging or temperature variation, etc. This circuit reduces the error, the difference between code values and real outputs of integrator, which is drawback of presented dual-slope tuning circuit and eliminates modulations of processing signals in integrated circuit due to fixed tuning codes during ordinary operation. This system is made up of simple integrator, A/D converter and digital control circuit and all capacitors are replaced by programed capacitor arrays in this system. This tuning circuit with 4 bit resolution achieves $-9.74{\sim}+9.68%$ of RC time constant error for 50% resistance variation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.10
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• pp.926-934
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• 2016

In this paper, we designed a compact frequency synthesizer with multi-function for Ka-band seeker. DDS(Direct Digital Synthesizer) is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and frequency up-converter are integrated in one module. Proposed frequency synthesizer provides precise detection and tracking waveform for low and high speed targets. It is observed that fabricated synthesizer performs $0.45{\mu}sec$ frequency switching time and -93.69 dBc/Hz phase noise at offset 1 kHz. The size of the synthesizer is kept within 120 mm width, 120 mm length and 22 mm height.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.11C
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• pp.1085-1097
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• 2009

We present a structure and design method of the D8PSK modem compatible with the VDL mode-2 standard and performance test results of the developed modem. In VDL mode-2, the raised cosine filter is used only in the transmitter and a general low pass filter is used in the receiver. Consequently, we can not achieve ISI reduction but can have better spectrum characteristics. Although there is 1~2 dB performance degradation with an un-matched filter compared to that with a matched filter, it is more important to minimize adjacent channel interference in narrow band communications. The transmit signal is generated digitally to avoid the problems(I/Q imbalance and DC offset etc.) of analog modulators. In addition the digital down converter using digital IF sampling technique is adopted for the receiver. This paper contains the overall configuration, design method and simulation results based in part on the previously proposed structures and algorithms. It is confirmed that the modem transmits and receives messages successfully at a speed of max. 870 km/h over ranges of up to 310 km through the ground and in-flight communication tests.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.11
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• pp.1627-1634
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• 2021

This paper introduces a low-power compact ADC circuit for analog Convolutional filter for low-power neural network accelerator SOC. While convolutional neural network accelerators can speed up the learning and inference process, they have drawback of consuming excessive power and occupying large chip area due to large number of multiply-and-accumulate operators when implemented in complex digital circuits. To overcome these drawbacks, we implemented an analog convolutional filter that consists of an analog multiply-and-accumulate arithmetic circuit along with an ADC. This paper is focused on the design optimization of a low-power 8bit SAR ADC for the analog convolutional filter accelerator We demonstrate how to minimize the capacitor-array DAC, an important component of SAR ADC, which is three times smaller than the conventional circuit. The proposed ADC has been fabricated in CMOS 65nm process. It achieves an overall size of 1355.7㎛², power consumption of 2.6㎼ at a frequency of 100MHz, SNDR of 44.19 dB, and ENOB of 7.04bit.