• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.21-30
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• 1998

In this paper, a digital current control system using a FPGA(Field Programmable Gate Array) was implemented, and the system was applied to an induction motor widely used as an industrial driving machine. The FPGA designed by VHDL(VHSIC Hardware Description Language) consists of a PWM(Pulse Width Modulation) generation block, a PWM protection block, a speed measuring block, a watch dog timer block, an interrupt control block, a decoder logic block, a wait control block and digital input and output blocks respectively. Dedicated clock inputs on the FPGA were used for high-speed execution, and an up-down counter and a latch block were designed in parallel, in order that the triangle wave could be operated at 40 MHz clock. When triangle wave is compared with many registers respectively, gate delay occurs from excessive fan-outs. To reduce the delay, two triangle wave registers were implemented in parallel. Amplitude and frequency of the triangle wave, and dead time of PWM could be changed by software. This FPGA was synthesized by pASIC 2SpDE and Synplify-Lite synthesis tool of Quick Logic company. The final simulation for worst cases was successfully performed under a Verilog HDL simulation environment. And the FPGA programmed for an 84 pin PLCC package was applied to digital current control system for 3-phase induction motor. The digital current control system of the 3 phase induction motor was configured using the DSP(TMS320C31-40 MHz), FPGA, A/D converter and Hall CT etc., and experimental results showed the effectiveness of the digital current control system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.6
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• pp.1330-1335
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• 2013

In recent years, the need to simultaneously transmit a variety of signals, such as DVI(Digital Visual Interface), audio, video, USB(Universal Serial Bus), LAN from the computer is required. So the cable complexity and scalability issues have been raised. In this paper, this signal can be distributed using a single USB cable, computer, video, audio, USB, LAN, one USB multi-signal transmission system was designed and implemented. USB multi-signal transmission was implemented in order to convert a single DVI, audio, and multiple USB, LAN, USB signal converter modules. This USB DVI port supports up to 1920 * 1080 resolution. USB multi-signal transmission system by sending multiple signals into a single cable installation costs of the various cable and using the replication feature of the screen, will provide schools and institutes, etc., providing the convenience of the river, and the scalability of computer peripheral ports.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.5
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• pp.1-9
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• 2012

In this paper, we presents the modeling and implementation of the DDS(Direct Digital synthesizer) driven offset PLL(Pghase Locked Loop) with DAC(Digital Analog Converter) for coarse tune. The PLL synthesizer was designed for minimizing the size and offset frequency and DDS technique was used for ultra low noise and fast lock up time, also DAC was used for coarse tune. The output phase noise was analyzed by superposition theory with the phase noise transfer function and noise source modeling. the phase noise prediction was evaluated by comparing with the measured data. The designed synthesizer has ultra fast lock time within 6 usec and ultra low phase noise performance of -120 dBc/Hz at 10KHz offset frequency.

• Journal of Digital Convergence
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• v.14 no.7
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• pp.193-200
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• 2016

Research and development of energy self-consumption introducing photovoltaic and energy storage system at home is very active. This system can manage the home energy in which it charges the electricity generated during the day and uses it during high electricity bills. However, it not yet made up the residential real-time pricing in Korea but it can reduce electricity usage to a certain target on the progressive. In order to introduce the home photovoltaic, it requires PCS(Power Conditioning System). This converts the direct current into alternating current by the electricity generated and used to perform charging and discharging of the energy storage system. The market for self-consumption smart home system is currently increasing because the interests of the general public about solar power, energy storage systems increased. The result of this study is installed on the room environment and the effect was analyzed on the assumption of real-time pricing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.37-47
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• 2006

This work proposes a 10b 25MS/s $0.8mm^2$ 4.8mW 0.13um CMOS A/D Converter (ADC) for high-performance wireless communication systems such as DVB, DAB and DMB simultaneously requiring low voltage, low power, and small area. A two-stage pipeline architecture minimizes the overall chip area and power dissipation of the proposed ADC at the target resolution and sampling rate while switched-bias power reduction techniques reduce the power consumption of analog amplifiers. A low-power sample-and-hold amplifier maintains 10b resolution for input frequencies up to 60MHz based on a single-stage amplifier and nominal CMOS sampling switches using low threshold-voltage transistors. A signal insensitive 3-D fully symmetric layout reduces the capacitor and device mismatch of a multiplying D/A converter while low-noise reference currents and voltages are implemented on chip with optional off-chip voltage references. The employed down-sampling clock signal selects the sampling rate of 25MS/s or 10MS/s with a reduced power depending on applications. The prototype ADC in a 0.13um 1P8M CMOS technology demonstrates the measured DNL and INL within 0.42LSB and 0.91LSB and shows a maximum SNDR and SFDR of 56dB and 65dB at all sampling frequencies up to 2SMS/s, respectively. The ADC with an active die area if $0.8mm^2$ consumes 4.8mW at 25MS/s and 2.4mW at 10MS/s at a 1.2V supply.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.2C
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• pp.209-216
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• 2009

The repeater for wireless broadband internet (Wibro) system using OFDM demands the short processing delay to eliminate inter-symbol interference resulted from the time delay greater than the guard time. Towards this, the total system delay of repeater is expected to be minimized as possible as it can without distorting signal quality. In general, the FIR-type of filter is commonly deployed as a channelization filter, but due to its large amount of coefficients for producing prerequisite filter response the excessive large time delay occurs. To withstand this problem, the paper proposes the method for designing IIR filter whose response almost identical to that of the original filter. Moreover, in order to linearize the phase response of the designed IIR filter, this paper also introduce the way of designing the all-pass filter to be cascaded works for linearizing phase response of the channelization as well as the de-channelization filter. To achieve the further improvement in linearization of the phase response and reduction of the overall complexity, this paper tries to transform the integrated IIR filter group into the structure in polyphase style. The computer simulation verifies that the integrated IIR filter group designed in this paper reveals the relatively short processing delay without harming the acceptible signal quality.

• Journal of the Korean Magnetics Society
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• v.24 no.4
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• pp.123-127
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• 2014

We developed a digital 3-axis flux-gate magnetometer for magnetic field signal measurement from warship during demagnetizing and degaussing processes. For the magnetometer design, we considered following points; the distance between magnetic field measurement station and magnetometer located under sea is about several 100 m, the magnetometer is exposed to magnetic field of ${\pm}1mT$ during demagnetizing process, and magnetometer is located under the sea about 30 m depth. To overcome long distance problem, magnetometer could be operated on wide input supply voltage range of 16~36 V using DC/DC converter, and for the data communication between the magnetometer and measurement station a RS422 serial interface was employed. To improve perming effect due to the ${\pm}1mT$ during demagnetizing process, magnetometer could be compensated external magnetic field up to ${\pm}1mT$ but magnetic field measuring rang is only ${\pm}100{\mu}T$. The perming effect was about ${\pm}2nT$ under ${\pm}1mT$ external magnetic field. The magnetometer was tested water vessel with air pressure up to 6 bar for the sea water pressure problems. Linearity of the magnetometer was better than 0.01 % in the measuring range of ${\pm}0.1mT$ and noise level was $30pT/\sqrt{Hz}$ at 1 Hz.

• Journal of Biomedical Engineering Research
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• v.28 no.3
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• pp.429-440
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• 2007

A coded excitation has been studied to improve the performance for ultrasound imaging in term of SNR, imaging frame rate, contrast to tissue ratio, and so forth. However, it requires a complicated arbitrary waveform transmitter for each active channel that is typically composed of a multi-bit Digital-to-Analog Converter (DAC) and a linear power amplifier (LPA). Not only does the LPA increase the cost and size of a transmitter block, but it consumes much power, increasing the system complexity further and causing a heating-up problem. This paper proposes an optimized 1.5bit fourth order sigma-delta modulation technique applicable to design an efficient arbitrary waveform generator with greatly reduced power dissipation and hardware. The proposed SDM can provide a required SQNR with a low over-sampling ratio of 4. To this end, the loop coefficients are optimized to minimize the quantization noise power in signal band while maintaining system stability. In addition, the decision level for the 1.5 bit quantizer is optimized for a given input waveform, which results in the SQNR improvement of more than 5dB. Computer simulation results show that the SQNR of a FM(frequency modulated) signal generated by using the proposed method is about 26dB, and the peak side-lobe level (PSL) of its compressed waveform on receive is -48dB.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.17 no.6
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• pp.51-57
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• 2017

In this paper, we designed a frequency synthesizer using DDS (Direct Digital Synthesizer) for Ka-band compact Radar. DDS is applied to generate various waveform and to cover high-speed frequency sweep. In order to reduce size, waveform generator and Ka band frequency up-converter are integrated in one module. Proposed frequency synthesizer provides LFM(Linear Frequency Modulation) waveform and Phase modulated FMCW (Frequency Modulation Continuous Wave) waveform. It is observed that fabricated synthesizer performs $0.191{\mu}sec$ frequency switching time and -89.16 dBc/Hz phase noise at offset 1 kHz.