• 대한전자공학회논문지
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• 제10권5호
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• pp.1-6
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• 1973

본논문은 자동급수기의 설계 및 제작연구를 한 것으로 digital scanning circuits를 이용하여 10개의 probe를 차례로 scanning하여 지표의 습도를 검출하여 reference level과 비교하여 필요한곳에 자동적으로 급수하도록 설계하였다. 이 system의 control을 위하여 main clock oscillator와 controloscillator를 사용하였고 control circuit로는 programmable unijunction transistor를 이용하여 reference level을 조절하게하여 임의의 원하는 습도에 급수하도록 하였다. 제작된 급수재는 모래의 습도가 6%에서 51%로 변화시키면서 실험하여 언제나 input level이 reference level보다 약 0.6V보다 높을때 완전동작하였으며 reference level은 임의로 조절할 수 있었다.

• 대한심미치과학회지
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• 제32권2호
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• pp.54-68
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• 2023

디지털 방법을 사용한 무치악의 임플란트 치료계획은 surgical guide design으로 구체화된다. Surgical guide를 제작할 때, 우리는 먼저 최종 보철의 형태를 가상공간에 구현한 후 이를 바탕으로 식립 계획을 구체화하게 된다. 그러나 완전무치악 환자는 치아배열의 기준이 없고 악간관계가 정립되어 있지 않아 최종 보철의 형태를 짐작하기 어려워 surgical guide를 만드는 데 어려움이 있다. 이때 기존의 만족스러운 총의치나 부분의치, 잔존치 등이 존재한다면 그 치아배열이 가상적인 최종 보철의 reference가 될 수 있다. 만약 이러한 reference가 부재하거나 만족스럽지 못하다면, 진단용 목적으로 총의치를 제작하되 이를 구내에서 검증하는 과정이 필요하다. 이러한 과정을 통해 surgical guide를 제작할지라도 구내 상황에 따라 implant의 위치가 계획한 것과 다르게 식립될 수 있으며, 만약 guide의 positioning이 잘못된다면 그 오차는 모든 implant의 위치를 변위시킬 수 있으므로 guide 수술이 오히려 재앙으로 다가올 수 있다. 본 기고에서는 치아 배열의 reference가 될 수 있는 자료들을 적절한 시기에 채득하여 이를 디지털 공간에 이전 및 통일된 좌표계로 정렬하는 방법에 대해 논의하고, 또한 이렇게 수립된 식립계획을 현실의 구강에 적은 오차로 이전 및 정렬하는 방법에 대해 소개하여 일관적이고 체계적인 무치악 가이드 디자인의 프로토콜 정립에 대해 의견 개진하려 한다.

• 한국컴퓨터정보학회논문지
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• 제23권8호
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• pp.1-7
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• 2018

Previous test equipment was bulky, took a long time to check, and was somewhat less economical. Since most of the checks were about analog signals, we preferred to check them using reference equipments. In this paper, a digital circuit design based on AITS is used to implement signals that can not utilize commercial measurement resources, and also designed and manufactured equipment that can inspect SRU. These test equipments were tested and evaluated by development, operation, and field evaluation, and they were installed to the Korean Field Force. This contributed to the improvement of operability by shortening the inspection time from 83.2 minutes to 7.8 minutes on average In addition, it did not utilize the reference equipment, so it could play a big role in lowering the mass production cost.

• Journal of Advanced Marine Engineering and Technology
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• 제16권4호
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• pp.50-59
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• 1992

The paper presents a digital speed control approach of induction motor systems by using a digital servo control method and a well-known second order differential equation as model. The basic concept of using the modeling equation stated in the above is induced from the control theory stand point such that we can describe usually the motor system connected by inverter, generator and load etc, just as a mechanical system to be controlled. The concept does not demand us the complicated vector-based modeling equation adopted in the traditional methods for the speed control of induction motor. Futhermore, the proposed speed control system can be treated as a single input and single output system. The effectiveness of the servo control system obtained by the above-mentioned design concept is illustrated by the experimental results in the presence of both step reference changes and load variations. It is observed from the experimental results that the steady state-error of the experimental set up becomes zero after some regulation time and the induction motor system is robust in spite of reference signal changes and load variations.

• 수산해양기술연구
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• 제28권1호
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• pp.27-38
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• 1992

The paper presents a digital speed control approach of induction motor systems by using a digital redesign method and adopting a well known 2nd order model as the system model equation. The basic concept using the modeling equation is induced from the control theory stand point such that we can describe usually the motor system connected by inverter, generator and load etc. just as a mechanical system to be controlled. The concept does not demand us the complicated vector-based modeling equation adopted in the traditional methods for the speed control of induction motor. The effectiveness of the servo control system composed by the above mentioned design concept is illustrated by the experimental results in the presence of step reference change and generator load variation. It is observed from the experimental results that the steady state error of the experimental set up becomes zero after some regulation time and the induction motor system is robust in spite of reference signal change and load variation of generator.

• 전력전자학회:학술대회논문집
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• 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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• pp.346-351
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• 1998

In design of a digital current controller for a 3-phase (3 ) voltage-source (VS) PWM converter, its conventional model, i.e., stationary or synchronous reference frame model, is used in obtaining its discretized version. It introduces, however, inherent errors since the following practical problems are not taken into consideration: the characteristics of the space vector-based pulse-width modulation (SVPWM) and the time delays in the process of sampling and computation. In this paper, the new hybrid reference frame model of the 3 VS PWM converter is proposed considering these problems. In addition, the direct digital current controller based on this model is designed without any prediction or extrapolation algorithm to compensate the time delay. So the control algorithm is made very simple. It represents no steady-state error in input current control and has the optimized transient responses. The validity of the proposed algorithm is proved by the computer simulation and experimental results.

• Journal of electromagnetic engineering and science
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• 제17권3호
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• pp.138-146
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• 2017

A phase-locked dielectric resonator oscillator (PLDRO) is an essential component of millimeter-wave communication, in which phase noise is critical for satisfactory performance. The general structure of a PLDRO typically includes a dual loop of digital phase-locked loop (PLL) and analog PLL. A dual-loop PLDRO structure is generally used. The digital PLL generates an internal voltage controlled crystal oscillator (VCXO) frequency locked to an external reference frequency, and the analog PLL loop generates a DRO frequency locked to an internal VCXO frequency. A dual loop is used to ease the phase-locked frequency by using an internal VCXO. However, some of the output frequencies in each PLL structure worsen the phase noise because of the N divider ratio increase in the digital phase-locked loop integrated circuit. This study examines the design aspects of an interconnected PLL structure. In the proposed structure, the voltage tuning; which uses a varactor diode for the phase tracking of VCXO to match with the external reference) port of the VCXO in the digital PLL is controlled by one output port of the frequency divider in the analog PLL. We compare the proposed scheme with a typical PLDRO in terms of phase noise to show that the proposed structure has no performance degradation.

• 한국산학기술학회논문지
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• 제4권2호
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• pp.63-70
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• 2003

본 논문에서는 반도체 제조장비의 핵심 부품 중에 하나인 질량유량제어기(MFC, Mass Flow Controller)클 설계하고 구현하였다 Microchip社의 마이크로콘트롤러(Microcontroller) PIC 16F876을 사용하여 개발된 MFC는 여러가지 문제점을 가진 아날로그(Analog) 방식의 MFC와 고가의 DSP(Digital Signal Processor) 및 고분해능의 AD변환기(Analog to Digital Convertor)를 사용하는 디지털 MFC의 장점을 혼합한 하이브리드형(Hybrid-Type)이다. 본 논문에서 개발된 MFC는 크게 센서부(Sensor Unit), 제어부(Control Unit), 구동기부(Actuator Unit)로 구성되었으며, 성능향상을 위한 자동보정(Automatic Calibration) 알고리즘과 표준테이블(Reference Table) 방식을 사용하였다.

• Journal of Electrical Engineering and Technology
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• 제10권4호
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• pp.1655-1666
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• 2015

This paper proposes a new approach of Field Programmable Gate Array (FPGA) controlled digital implementation of shunt active power filter (SAPF) under steady state and dynamic operations. Typical implementations of SAPF uses microprocessor and digital signal processor (DSP) but it limited for complex algorithm structure, absence of feedback loop delays and their cost can be exceed the benefit they bring. In this paper, the hardware resources of an FPGA are configured and implemented in order to overcome conventional microcontroller or digital signal processor implementations. This proposed FPGA digital implementation scheme has very less execution time and boosts the overall performance of the system. The FPGA controller integrates the entire control algorithm of an SAPF, including synchronous reference frame transformation, phase locked loop, low pass filter and inverter current controller etc. All these required algorithms are implemented with a single all-on chip FPGA module which provides freedom to reconfigure for any other applications. The entire algorithm is coded, processed and simulated using Xilinx 12.1 ISE suite to estimate the advantages of the proposed system. The coded algorithm is also defused on a single all-on-chip Xilinx Spartan 3A DSP-XC3SD1800 laboratory prototype and experimental results thus obtained match with simulated counterparts under the dynamic state and steady state operating conditions.

• Journal of the Optical Society of Korea
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• 제13권2호
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• pp.245-250
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• 2009

We propose a digital holographic interference analysis method based on a 2-frame phase-shifting technique for measuring an optical mirror surface. The technique using 2-frame phase-shifting digital interferometry is more efficient than multi-frame phase-shifting techniques because the 2-frame method has the advantage of a reduced number of interferograms, and then takes less time to acquire the wanted topography information from interferograms. In this measurement system, 2-frame phase-shifting digital interferograms are acquired by moving the reference flat mirror surface, which is attached to a piezoelectric transducer, with phase step of 0 or $\pi$/2 in the reference beam path. The measurements are recorded on a CCD detector. The optical interferometry is designed on the basis of polarization characteristics of a polarizing beam splitter. Therefore the noise from outside turbulence can be decreased. The proposed 2-frame algorithm uses the relative phase difference of the neighbor pixels. The experiment has been carried out on an optical mirror which flatness is less than $\lambda$/4. The measurement of the optical mirror surface topography using 2-frame phase-shifting interferometry shows that the peak-to-peak value is calculated to be about $0.1779{\mu}m$, the root-mean-square value is about $0.034{\mu}m$. Thus, the proposed method is expected to be used in nondestructive testing of optical components.