• 전기의세계
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• v.26 no.3
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• pp.63-68
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• 1977

In this paper, the theory of pulse frequency modulated DC/DC power converter to obtain constant output voltage for all input voltage changes is discussed. The switch controller consisting of integrator and comparator determines the ON time of power switch-Thyristor-by the error between the load voltage and a load reference voltage. Resulting voltage and current waveforms have been studied theoretically in detail and verified experimentally for a resistive and inductive load condition. State equations for voltages and currents using binary logic variables are computed by digital computer. Comparison of these withe oscillograms obtained from an experimental model shows very close agreement.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.986-989
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• 1999

An 12bit current-mode folding and interpolation analog to digital converter (ADC) with multiplied folding amplifiers is proposed in this paper. A current - mode multiplied folding amplifier is employed not only to reduced the number of reference current source, but also to decrease a power dissipation within the ADC. The designed ADC fabricated by a 0.6${\mu}{\textrm}{m}$ n-well CMOS double metal/single poly process. The simulation result shows the power dissipation of 280㎽ with a power supply of 5V.

• Journal of the Korean Data and Information Science Society
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• v.16 no.4
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• pp.1119-1128
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• 2005

The Bayes factors with improper noninformative priors are defined only up to arbitrary constants. So it is known that Bayes factors are not well defined due to this arbitrariness in Bayesian hypothesis testing and model selections. The intrinsic Bayes factor and the fractional Bayes factor have been used to overcome this problem. In this paper, we suggest a Bayesian hypothesis testing based on the intrinsic Bayes factor and the fractional Bayes factor for the comparison of two lognormal variances. Using the proposed two Bayes factors, we demonstrate our results with some examples.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.677-678
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• 2008

In this study, the method for the measurement of harmonics at nonsinusodial signal, which utilizes two synchronized high precision digital multimeters has been developed. The harmonics of voltage and current waveforms were computed from the acquired digitize samples through the DMMs and using developed software which based on FFT algorithm. The system can be used as a reference system to calibrate harmonic analyzers.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.32 no.2
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• pp.59-64
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• 1983

This paper deals with the transient energy method of transient stability analysis of multi-machine power system by improving the transfer conductance, the kinetic energy and the critical transient energy. The tranfer conductance is considered more correctly, the generators of system are seperated to two states (critical and the rest state)and the correction term of critical transient energy (to reference point) is added. This analysis is performed by digital computer simulation and the application of this method to two model systems has shown its superiority to other available methods.

• Digital Contents
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• no.11 s.126
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• pp.116-118
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• 2003

미국의 ADL(Advance Distributed Learning)에서 제안한 스콤(SCORM; Sharable Content Object Reference Model)은 2000년 미국 국방부에서 발주한 6억달러에 이르는 e-러닝(e-Learning) 구축 입찰 계약에서 가이드라인으로 쓰여졌다. 용역 입찰 제안서에 스콤을 기초로 해 e-러닝 시스템을 구축하겠다는 내용이 명시돼야만 입찰에 참여할 수 있었던 것이다. 현재 제안된 e- 러닝 기술표준안들에 대한 국제인증 여부와 관계없이 e-러닝 실수요자 및 공급자의 움직임에 따라 이러한 추세는 향후 더욱 확대될 전망이다. 이 글에서는 실질적인 국제 표준으로 가장 근접해 있는 스콤의 내용 및 기술적 특징에 대해 설명하고자 한다.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.36 no.2
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• pp.107-113
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• 1987

A complete design of a new digital control circuit for a three-phase controlled rectifier is presented. The circuit consists of a gating signal generating ROM, down counter and adder. Proposed scheme is simple and quite adequate to the microprocessor-based digitally controlled systems. The basic principle and operation characteristics of the circuit are described and experimental-results show good dynamic performance. Synchronization problem with noisy reference is also discussed. The basic phylosophy developed can be extended to the other phase control system, e.g., cycloconverters, ac voltoge controllers, etc.

• Nuclear Engineering and Technology
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• v.55 no.10
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• pp.3639-3647
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• 2023

This paper defines a 3D full core neutronics benchmark which is based on the NuScale small modular reactor (SMR) concept. The paper provides a detailed description of the NuScale-like core, a list of expected outputs, and a reference solution to the benchmark exercises obtained with the Monte Carlo code Serpent. The benchmark was developed in the framework of the Euratom McSAFER project and can be used for verification of computational chains dedicated to 3D full-core neutronics simulations of water cooled SMRs. The paper is supplemented with a digital data set to ease the modeling process.

• Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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• v.27 no.1
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• pp.677-682
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• 2009

According to the revised law of survey, all the geographic information data including 1/1,000 digital topographic maps have to be converted to world geodetic reference system by the end of 2009. National Geographic Information Institute (NGII) formulated the policy to promote the conversion from local geodetic reference system to world geodetic reference system. However, the current conversion rate is lower than planned due to some impeding factors. Therefore, in this paper, those impeding factors are investigated and then efficient conversion strategies are established and provided. The research involves the validation of affine transformation, the determination of critical value for outlier detection and optimal number of common control points for coordinate conversion, and the treatment of old and new control points.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.9
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• pp.54-61
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• 2016

A 6-Gbps single-ended receiver with a linear equalizer and a self-reference generator is proposed for a high-speed interface with the double data rate. The proposed single-ended receiver uses a common gate amplifier to increase a voltage gain for an input signal with low voltage level. The continuous-time linear equalizer which reduces gain to the low frequencies and achieves high-frequency peaking gain is implemented in the common gate amplifier. Furthermore, a self-reference generator, which is controlled with the resolution 2.1 mV using digital averaging method, is implemented to maximize the voltage margin by removing the offset noise of the common gate amplifier. The proposed single-ended receiver is designed using a 65-nm CMOS process with 1.2-V supply and consumes the power of 15 mW at the data rate of 6 Gbps. The peaking gain in the frequency of 3 GHz of the designed equalizer is more than 5 dB compared to that in the low frequency.