• The Transactions of the Korea Information Processing Society
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• v.3 no.5
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• pp.1187-1197
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• 1996

In this work, two-dimensional FIR digital filter is designed and simulated using research and educational CAD tools. The two-dimensional digital filter consists mainly of one-dimensional digital filter and line memory. To speed up one-dimensional digital filter, multiplications are carried out on the basis of hardwired-shifting methods by the digital filter coefficients represented in CSD formats, while carry-save adder and Manchester adder are used in addition. It is found that the designed digital filter operates up to 30 Mhz in VHDL simulation and operates normally in IRSIM simulation for the layout made by Berkeley CAD tools.

• Journal of the Optical Society of Korea
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• v.19 no.5
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• pp.456-466
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• 2015

We investigated an anti-aliasing (AA) filter for digital camera photography by which the excessively high-frequency components of the image signal are suppressed to avoid the aliasing effect. Our optomechanical AA filter was implemented by applying rapid relative motions to the imaging sensor. By the engineered motion blur of the mechanical dithers, the effective point-spread function (PSF) of the imaging system could be tailored to reject the unwanted high-frequency components of the image. For optimal operations, we developed a spiral filter motion protocol that could produce a Gaussian-like PSF. We experimentally demonstrated that our AA filter provides an improved filtering characteristic with a better compromise of the rejection performance and the signal loss. We also found that the pass band characteristic can be enhanced further by a color-differential acquisition mode. Our filter scheme provides a useful method of digital photography for low-error image measurements as well as for ordinary photographic applications where annoying $moir{\acute{e}}$ patterns must be suppressed efficiently.

• The Transactions of the Korean Institute of Power Electronics
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• v.26 no.5
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• pp.307-314
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• 2021

Even though the LCL filters have superior harmonic attenuation ability to L filters, stability has always been an issue. The system could be unstable because of the resonance phenomenon, especially when digital controller is used. Adding a notch filter to the compensator is one approach to solve the problem. Resonance phenomenon can be inhibited by aligning notch frequency to system resonance frequency. However, resonance frequency variation can be obtained because the actual system has a nonstationary characteristic. Therefore, the system could be unstable, where the system parameters are changed when the conventional notch filter is used. An adaptive digital notch filter that stabilizes the system even system parameters are changed. Simulation and experiment results are provided to verify the validity of the proposed adaptive filter.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.40 no.12
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• pp.155-160
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• 2003

Owing to the advances in ADC and DSP technologies, signals in If band, which once had to be processed in analog technology, can new be digitally processed. This is referred to as "Digital IF" or "Digital Radio", which is a preliminary stage of SDR. Applying the digital radio technology to a multi-carrier receiver design, a processing gain is generated through an over-sampling of input data. In the digital receiver, decimation is performed for reducing the computational complexity CIC and half band filter is used together with the decimation as an anti-alising filter. The CIC filter, however, should introduce the roll-off phenomenon in the passband, which causes the receiving performance to be considerably degraded due to the distorted Passband flatness of receiving filter. In this paper, we designed a CIC roll-off compensation filter for W-CDMA digital receiver. The performance of the proposed compensation filter is confirmed through computer simulations in such a way that the BER is minimized by compensating the roll-off characteristics.off characteristics.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.1
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• pp.49-55
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• 2003

The use of digital filters in the signal process field is increasing rapidly with development of the modern industrial society. Especially, detail processors, Y/C separators, ghost removing filters, standard converters (NTSC to PAL or PAL to NTSC) and noise reducers, all of which use digital filters, tend to be used in digital video and audio processing, CATV and various communication fields. Generally, there are two different digital filters, the Rf (infinite impulse response) filter and the FIR (finite impulse response) filter in digital filter. In this paper, we have designed FIR filter which has the phase linearity and the easiness of creation. In the design of the FIR digital filter, the window function is used to alleviate the ripples caused by Gibbs Phenomenon around the cut off frequency of the band pass. But there're some problems to choose proper window function for the design destination due to its fixed values. Therefore, in this paper, we designed a modified Hanning window with new parameter which is adaptively chosen corresponding to design objectives. The digital filter was simulated to prove the validity of the model and it was compared with the Hamming, the Manning, the Blacknan and the Kaiser window function. And we have used peak side-lobe and transient characteristics as standard of judgement.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.11
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• pp.3087-3093
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• 2009

Digital filters are indispensible element in digital signal processing area. The performance of digital filter based on adding and multiplying operation, such as computational speed and power consuming is determined by the orders and coefficients of filter which has on effect area of semiconductor chip when it is implemented by VLSI technology. In this research, in order to performance improvement of digital filter, we proposed the algorithm to speed-up the operation of digital filter associated with the minimum signed digit representation of binary number system and method to simplify the digital filter design associated with common subexpression elimination. The performance of proposed method is evaluated by the computational speed and design-simplicity by experimental implemented digital filter on FPGA.

• ETRI Journal
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• v.35 no.4
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• pp.697-705
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• 2013

Emerging trends in the area of digital very large scale integration (VLSI) signal processing can lead to a reduction in the cost of the cochlear implant. Digital signal processing algorithms are repetitively used in speech processors for filtering and encoding operations. The critical paths in these algorithms limit the performance of the speech processors. These algorithms must be transformed to accommodate processors designed to be high speed and have less area and low power. This can be realized by basing the design of the auditory filter banks for the processors on digital VLSI signal processing concepts. By applying a folding algorithm to the second-order digital gammatone filter (GTF), the number of multipliers is reduced from five to one and the number of adders is reduced from three to one, without changing the characteristics of the filter. Folded second-order filter sections are cascaded with three similar structures to realize the eighth-order digital GTF whose response is a close match to the human cochlea response. The silicon area is reduced from twenty to four multipliers and from twelve to four adders by using the folding architecture.

• Journal of the Semiconductor & Display Technology
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• v.20 no.3
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• pp.71-76
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• 2021

Digital decimation filters are used in various digital signal processing systems using ADCs, including digital communication systems and sensor network systems. When the sampling rate of digital data is reduced, aliasing occurs. So, an anti-aliasing filter is necessary to suppress aliasing before down-sampling the data. Since the anti-aliasing filter has to have a sharp transition band between the passband and the stopband, the order of the filter is very high. However, as the order of the filter increases, the complexity and area of the filter increase, and more power is consumed. Therefore, in this paper, we propose two types of decimation filters, focusing on reducing the area of the hardware. In both cases, the complexity of the circuit is reduced by applying the required down-sampling rate in two times instead of at once. In addition, CIC decimation filters without a multiplier are used as the decimation filter of the first stage. The second stage is implemented using a CIC filter and a down sampler with an anti-aliasing filter, respectively. It is designed with Verilog-HDL and its function and implementation are validated using ModelSim and Quartus, respectively.

• Journal of the Institute of Convergence Signal Processing
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• v.9 no.1
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• pp.62-74
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• 2008

In this paper, we would like to propose the design of symmetric digital filter core in order to use in the radio astronomy. The function of FIR filter core would be designed by VHDL code required at the Data Acquisition System (DAS) of Korean VLBI Network (KVN) based on the FPGA chip of Vertex-4 SX55 model of Xilinx company. The designed digital filter has the symmetric structure to increase the effectiveness of system by sharing the digital filter coefficient. The SFFU(Symmetric FIR Filter Unit) use the parallel processing method to perform the data processing efficiently by using the constrained system clock. In this paper, therefore, for the effective design of SFFU, the Unified Synthesis software ISE Foundation and Core Generator which has excellent GUI environment were used to overall IP core synthesis and experiments. Through the synthesis results of digital filter core, we verified the resource usage is less than 40% such as Slice LUT and achieved the maximum operation frequency is more than 260MHz. We also confirmed the SFFU would be well operated without error according to the SFFU simulation result using the Modelsim 6.1a of Mentor Graphics Company. To verify the function of SFFU, we carried out the additional simulation experiments using the pseudo signal to the Matlab software. From the comparison experimental results of simulation and the designed digital FIR filter, we confirmed the FIR filter was well performed with filter's basic function. So we verified the effectiveness of the designed FIR digital filter with symmetric structure using FPGA and VHDL.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.3
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• pp.11-17
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• 2010

Multi-standard, multi-band, multi-service system to ensure a flexible interface between the SDR (Software Defined Radio) technology for the implementation of the Stability and Low-Power, Low-Calcualrion DDC (Digital Down Conversion) technology is essential. DDC technology consists of a digital channel filter. This is a typical digital filter because of the limited fisheries are vulnerable to overflow and rounding errors are drawbacks. In this paper, we overcome this disadvantage, we propose the structure of the DDC. The way WDF (Wave Digital Filter) Structural rounding error due to the structural resistance to noise. Therefore, This is the useful structure when the filter coefficients's word length is short. In addition, since IIR filters based on FIR filters based on the amount of computation is reduced because fewer than filter's tap. The proposed structure is used in DDC that CIC (Cascaded Integrator Comb) filter, WDF, IFOP (Interpolated Fourth-Order Polynomials) were analyzed with respect to, the results were confirmed by computer simulation.