• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.8C
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• pp.782-791
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• 2002

This paper discusses a far-end crosstalk (FEXT) canceller for twisted-pair transmission. Many twisted-pair systems such as fiber-to-the-curb (FTTC), very high-speed digital subscriber line (VDSL), and high-speed LAN systems, use frequency-division duplexing (FDD) for duplex transmission. It is shown that the maximum reach of FDD twisted-pair system is limited by the performance of its upstream channel, which is located at higher frequencies than the downstream channel. In order to improve the performance of such FDD transceiver, FEXT cancellation is introduced for the channel at higher frequencies. A system arrangement and its blind start-up procedure are studied when the FEXT canceller and equalizer are jointly adapted to combat channel intersymbol interference (ISI), FEXT, and other additive noise. The initial convergence and the steady-state behavior of the proposed twisted-pair system without requiring transmission of an ideal training sequence are investigated. Measured characteristics as well as analytical model of the FEXT channel are used to estimate the time span needed for the FEXT canceller. It is also shown that the memory span for the FEXT canceller is almost independent of the channel, thus making our results useful for the twisted-pair system over all different channels.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.1A
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• pp.167-177
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• 2000

In this paper, a new algorithm to design a time-domain equalizer (TEQ) for an xDSL system employing the discrete multitone (DMT) modulation is proposed. The proposed algorithm, derived by neglecting the terms whichdo not affect the performance of a DMT system in ARMA modeling, is shown to have similar performance tothe previous TEQ algorithms such as matrix inverse algorithm, fast algorithm, iterative algorithm, and inversepower method, even with the significantly lower computational complexity. In addition, since the proposedalgorithm requires only the received signal, the information on the channel impulse response or training sequenceis not needed. It is also shown that for the case where bridged tap is not included, the number of TEQ tapsrequired can be reduced to half(from 16 to 8) without affecting the overall performance. The performances of theproposed and previous TEQ algorithms are compared by applying them to ADSL environment.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.12
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• pp.60-69
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• 2000

This paper describes a single-chip full-custom implementation of pipelined adaptive decision-feedback equalizer(PADFE) using a 0.25-${\mu}m$ CMOS technology for wide-band wireless digital communication systems. To enhance the throughput rate of ADFE, two pipeline stages are inserted into the critical path of the ADFE by using delayed least-mean-square(DLMS) algorithm. Redundant binary (RB) arithmetic is applied to all the data processing of the PADFE including filter taps and coefficient update blocks. When compared with conventional methods based on two's complement arithmetic, the proposed approach reduces arithmetic complexity, as well as results in a very simple complex-valued filter structure, thus suitable for VLSI implementation. The design parameters including pipeline stage, filter tap, coefficient and internal bit-width, and equalization performance such as bit error rate (BER) and convergence speed are analyzed by algorithm-level simulation using COSSAP. The single-chip PADFE contains about 205,000 transistors on an area of about $1.96\times1.35-mm^2$. Simulation results show that it can safely operate with 200-MHz clock frequency at 2.5-V supply, and its estimated power dissipation is about 890-mW. Test results show that the fabricated chip works functionally well.

• Journal of KIISE:Computer Systems and Theory
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• v.32 no.2
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• pp.55-67
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• 2005

Separation between computation and communication in system design allows the system designer to explore the communication architecture independently of component selection and mapping. In this paper we present an iterative two-step exploration methodology for bus-based on-chip communication architecture and memory allocation, assuming that memory traces from the processing elements are given from the mapping stage. The proposed method uses a static performance estimation technique to reduce the large design space drastically and quickly, and applies a trace-driven simulation technique to the reduced set of design candidates for accurate Performance estimation. Since local memory traffics as well as shared memory traffics are involved in bus contention, memory allocation is considered as an important axis of the design space in our technique. The viability and efficiency of the proposed methodology arc validated by two real -life examples, 4-channel digital video recorder (DVR) and an equalizer for OFDM DVB-T receiver.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1231-1243
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• 1997

Digital satellite communication channels have nonlinearities with memory due to saturation characteristics of traveling wave tube amplifier in the satellite and transmitter/receiver linear filters. In this paper, we propose a network structure and a learning algorithm for complex pi-sigma network (CPSK) and exploit CPSN in the problem of equalization of nonlinear satellite channels. The proposed CPSN is a complex-valued extension of real-valued pi-sigma network that is a higher-order feedforward network with fast learning while greatly reducing network complexity by utilizing efficient form of polynomials for many input variables. The performance of the proposed CPSN is demonstrated by computer simulations on the equalization of complex-valued QPSK input symbols distorted by a nonlinear channel modeled as a Volterra series and additive noise. The results indicate that the CPSN shows good equalization performance, fast convergence, and less computations as compared to conventional higher-order models such as Volterra filters.

• The Journal of the Acoustical Society of Korea
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• v.23 no.2
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• pp.117-124
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• 2004

In this paper, we have been implemented the QPSK-based underwater transmission systems using DSP in order to transmit the underwater image data. We have adopted a BDPA (Block Data Parallel Architecture) to control multiple DSPs used in the transmitter and receiver in order to transmit the image data in real-time. We also have developed GUI software in order to drive and to debug the implemanted system in real-time. We have executed open sea tests in order to analyze the performance of the implemented system at East Sea near Kosung in Kangwon-Do. As a result of these experiments, it has been demonstrated that 10 kbps image data can be received without errors at 30m and 80m depth points, while the distance between the transmitter and the receiver is up to 20m.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.06a
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• pp.754-757
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• 2007

In this paper, we present an implementation and it's real-sea test of an underwater acoustic data communication system, which allows the system to reduce complexity and increase robustness in time variant underwater environments. For easy adaptation to complicated and time-varying environments of the ocean, all-digital transmitter and receiver systems were implemented. For frame synchronization the CAZAC sequence was used, and QPSK modulation/ demodulation method with carrier frequency of 25kHz and a bandwidth of 5kHz were applied to generate 10kbps transmission rate including overhead. To improve transmission quality, we used several techniques and algorithms such as adaptive beamforming, adaptive equalizer, and convolution coding/Viterbi decoding. for the verification of the system performance, measurement of BER has been done in a very shallow water with depth of 8m at JangMok, Geoje. During the experiment, image data were successfully transmitted up to about 7.4km.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.5
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• pp.27-33
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• 2011

In digital communication system that the Modified Constant Modulus Algorithm (MCMA) reduced the use of the adaptive equalization algorithm to combat the Inter-symbol Interference (ISI). MCMA is relatively brief operation. The major point of MCMA that it only achieves moderate convergence rate and steady state mean square error (MSE). In this paper suggest, MCMA equalization improve the performance with parallel structure. It combines Modified Constant Modulus Algorithm(MCMA) and Modified Decision Directed(MDD) algorithm. By exploiting the inherent structural relationship between the 4-QAM signal's coordinates and 16-QAM signal's coordinates, another style of cost function for Modified Constant Modulus Algorithm(MCMA) is defined and If it happen to offset of received signals and MCMA is poor performance in order to overcome this because the paper combines apply for MCMA and MDD(Modified Decision Direct) algorithm. By computer simulation, we confirmed that the proposed PMCMA-MDD algorithm has the fater convergence rate and steady mean square error than the conventional MCMA.

• Journal of Korea Multimedia Society
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• v.12 no.3
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• pp.329-334
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• 2009

When an optical disc is being played. the pick-up converts light to analog signal at first. The analog signal is equalized for removing the inter-symbol interference and then the equalized analog signal is converted into the digital signal for extracting the synchronized data and clock signals. There are a lot of algorithms that minimize the BER in extracting the synchronized data and clock when high. density optical disc like BD is being played in low speed. But if the high-density optical disc is played in high speed, it is difficult to adopt the same extraction algorithm to data PLL and PRML architecture used in low speed application. It is because the signal with more than 800MHz should be processed in those architectures. Generally, in the 0.13-${\mu}m$ CMOS technology, it is necessary to have the high speed analog cores and lots of efforts to layout. In this paper, the parallel data PLL and PRML architecture, which enable to process in BD 8x speed of the maximum speed of the high-density optical disc as the extracting data and clock circuit, is proposed. Test results show that the proposed architecture is well operated without processing error at BD 8x speed.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.9
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• pp.818-823
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• 2016

Millimeter wave (mm-wave) communication systems provide high data rates owing to the large bandwidths available at mm-wave frequencies. Recently, analogue and digital combined beamforming, namely "hybrid beamforming" has drawn attentions owing to its ability to realize the required link margins in mm-wave systems. Taking into account the radio frequency (RF) hardware limitations, such as the analogue phase shifter gain constraint and the low resolution of the phase controller, we introduce an uplink hybrid beamforming system that includes discrete Fourier transform (DFT) based "fixed" analogue beamforming. We adopt a zero-forcing (ZF) multiple-input multiple-output (MIMO) equalizer to eliminate the uplink inter-user interferences. Moreover, to improve the sum-rate performances, we propose a transmit beam selection algorithm which makes the uplink effective channels, i.e., the beamformed channels, become near orthogonal. The effectiveness of the proposed beam selection algorithm was verified through numerical simulations.