• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2005.11a
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• pp.39-44
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• 2005

A broadband DC to 40 GHz 5-bit MMIC digital attenuator has been developed. The ultra broadband attenuator has been achieved by newly inserted the transmission lines in conventional Switched-T attenuator and the optimization of the transmission line parameters. Momentum was employed in design for an accurate performance prediction at high frequencies and Monte Carlo analysis was applied to verify performance stability against the MMIC process variation. The attenuator has been fabricated with 0.15 $\mu$m GaAs pHEMT process. This attenuator has 1 dB resolution and 23 dB dynamic range. High attenuation accuracy has been achieved over all attenuation range and full 40 GHz bandwidth with the reference state insertion loss of less than 6 dB at 20 GHz. The input and output return losses of the attenuator are better than 14 dB over all attenuation states and frequencies.

• Journal of the Korea Institute of Military Science and Technology
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• v.12 no.4
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• pp.452-459
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• 2009

A 6-bit MMIC digital attenuator applicable to X-band TR module has been developed by using $0.5{\mu}m$GaAs pHEMT processes. The Switched-T attenuator scheme and the switched-path attenuator scheme were adopted to obtain low insertion loss and small phase variation, respectively. Resistors and transmission lines are optimized to achieve the digital attenuator with high attenuation accuracy and small phase variation. The digital attenuator has RMS error of 0.4dB, resolution of 0.5dB and dynamic range of 31.5dB. The measurement results show that in-out VSWRs are less than 1.5, phase variation is from -7 to +2 degrees and IIP3 is 36.5dBm.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.101-109
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• 2006

A broadband, DC to 40 GHz 5-bit MMIC digital attenuator has been developed. The ultra broadband attenuator has been achieved by adding transmission lines in the conventional Switched-T attenuator and optimizing the transmission line parameters. Momentum simulation was performed in design for accurate performance prediction at high frequencies and Monte Carlo analysis was applied to verify the performance stability against the MMIC process variation. The attenuator has been fabricated with $0.15\;{\mu}m$ GaAs pHEMT process. This attenuator has 1 dB resolution and 23 dB dynamic ranges. High attenuation accuracy has been achieved over all attenuation ranges and 40 GHz bandwidth with the reference state insertion loss of less than 6 dB at 20 GHz. The input and output return losses of the attenuator are better than 14 dB over all attenuation states and frequencies. The measured IIP3 of the attenuator is 33 dBm.

• ETRI Journal
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• v.35 no.4
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• pp.638-643
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• 2013

This paper presents a 5-bit digital step attenuator (DSA) using a commercial 0.18-${\mu}m$ silicon-on-insulator (SOI) process for the wideband phased array antenna. Both low insertion loss and low root mean square (RMS) phase error and amplitude error are achieved employing two attenuation topologies of the switched path attenuator and the switched T-type attenuator. The attenuation coverage of 31 dB with a least significant bit of 1 dB is achieved at DC to 20 GHz. The RMS phase error and amplitude error are less than $2.5^{\circ}$ and less than 0.5 dB, respectively. The measured insertion loss of the reference state is less than 5.5 dB at 10 GHz. The input return loss and output return loss are each less than 12 dB at DC to 20 GHz. The current consumption is nearly zero with a voltage supply of 1.8 V. The chip size is $0.93mm{\times}0.68mm$, including pads. To the best of the authors' knowledge, this is the first demonstration of a low phase error DC-to-20-GHz SOI DSA.

• Proceedings of the Optical Society of Korea Conference
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• 2005.02a
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• pp.292-295
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• 2005

Variable optical attenuators (VOA) made of low-loss fluorinated polymers are demonstrated which shows a low operating power less than 30 mW due to the superior thermo-optic effect of polymer material and a low insertion loss less than 1.0 dB by incorporating highly fluorinated polymers to reduce the absorption loss at 1550 nm. An attenuator-integrated low-crosstalk polymeric digital optical switch (DOS) is also demonstrated. The switch and attenuator shares a single connected electrode which is controlled by a single current source. Due to the simple structure of the integrated attenuator, the device length is reduced to 1 cm so as to provide low insertion loss of 0.8 and 1.1 dB for 1300 and 1550 nm, respectively. The attenuator radiates remained optical signal on the switch-off branch in order to decrease the switching crosstalk to be less than -70 dB with an applied electrical power of 200 mW.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.15 no.5
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• pp.3079-3085
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• 2014

This paper suggests a power level controllable frequency up-converter which is designed and fabricated using both the filtering technology consisted with only passive devices and a multi-level digital attenuator. The suggested frequency up-converter simultaneously realizes the low power consumption and the low cost model. Because of the possibility for controlling power levels, it is possible to use the suggested frequency up-converter for wide spectral range. According to the experimental results, the average gain value of 0.75dB is obtained for the bandwidth of 160MHz at the center frequency of 1,200MHz. Especially, it is confirmed that the power level can be controlled from 10 to -21.5dBm through the digital attenuator.

• ETRI Journal
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• v.33 no.2
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• pp.275-278
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• 2011

This letter presents a polymer $1{\times}2$ thermo-optic totalinternal-reflection digital optical switch (TIR-DOS) with an index contrast of 1.5%-${\delta}$ operating at low power consumption. The structure of our $1{\times}2$ TIR-DOS was created by adding a reflection port to that of a conventional multimode filtering variable optical attenuator. To improve the total-internalr-eflection efficiency, a heater offset was applied to the crossing region of multimode waveguides of the TIR-DOS. The fabricated $1{\times}2$ TIR-DOS shows a low electrical power consumption of 18 mW for an on-off ratio of 35 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.1
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• pp.60-68
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• 2016

This paper presents a 6~18 GHz 7-bit digital-controlled attenuator. The proposed attenuator is based on switched-T architecture, but no inductor is used for minimum chip size. The designed attenuator was fabricated using $0.18{\mu}m$ CMOS process, and characterized using on-wafer testing setup. The resolution(minimum attenuation step) and the maximum attenuation range of the attenuator were measured to be 0.22 dB and 28 dB, respectively. The measured RMS attenuation error and the RMS phase error for 6~18 GHz were less than 0.26 dB and $3.2^{\circ}$, respectively. The reference state insertion loss was less than 12.4 dB at 6~18 GHz. The measured input and output return losses were better than 9.4 dB over all frequencies and attenuation states. The chip size is $0.11mm^2$ excluding pads.

• Journal of Satellite, Information and Communications
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• v.3 no.1
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• pp.1-7
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• 2008

This Paper studied the design and measured results of a flight model for Ku-Band Linearized Channel Amplifier (LCAMP) for communication satellite onboard system. All MMICs, i.e. Variable Gain Amplifier (VGA), Variable Voltage Attenuator (VVA) with analog/digital attenuator, Branch line Hybrid Coupler and Detector for Pre-distorter are fabricated using Thin-Film Hybrid process. The performance of the fabricated module is verified through Radio Frequency circuit simulations and electrical function test in space environment for flight model at 12.25 to 12.75 GHz.

• ETRI Journal
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• v.40 no.6
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• pp.693-698
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• 2018

This paper presents a true-time delay (TTD) using a commercial $0.13-{\mu}m$ CMOS process for wideband phased-array antennas without the beam squint. The proposed TTD consists of four wideband distributed gain amplifiers (WDGAs), a 7-bit TTD circuit, and a 6-bit digital step attenuator (DSA) circuit. The T-type attenuator with a low-pass filter and the WDGAs are implemented for a low insertion loss error between the reference and time-delay states, and has a flat gain performance. The overall gain and return losses are >7 dB and >10 dB, respectively, at 2 GHz-18 GHz. The maximum time delay of 198 ps with a 1.56-ps step and the maximum attenuation of 31.5 dB with a 0.5-dB step are achieved at 2 GHz-18 GHz. The RMS time-delay and amplitude errors are <3 ps and <1 dB, respectively, at 2 GHz-18 GHz. An output P1 dB of <-0.5 dBm is achieved at 2 GHz-18 GHz. The chip size is $3.3{\times}1.6mm^2$, including pads, and the DC power consumption is 370 mW for a 3.3-V supply voltage.