• Journal of the Institute of Electronics Engineers of Korea CI
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• v.37 no.3
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• pp.45-55
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• 2000

In this paper, we proposed the hardware architecture of wavelet transform digital filter for an image processing. Filter bank pyramid algorithm is used for wavelet transform and each fillet is implemented by the FIR filter. For DWT computation, because the memory controller is implemented by hardware, we can efficiently process the multisolution decomposition of the image data only input the parameter. As a result of the image Processing in this paper, 33㏈ PSNR has been obtained on 512$\times$512 B/W image due to 11-bit mantissa processing in FPGA Implementation. And because of using QMF( Quadrature Mirror Filter) properties, it reduces half number of the multiplier needed DWT(Discrete Wavelet Transform) computation so the hardware size is reduced largely. The proposed scheme can increase the efficiency of an image Processing as well as hardware size reduced. The hardware design proposed of DWT fillet bank is synthesized by VHDL coding and then the test board is manufactured, the operating Program and the application Program are implemented using MFC++ and C++ language each other.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.15 no.3
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• pp.99-105
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• 2015

This paper deals with the mMMA (modified MMA) which possible to improving the convergence speed that employing the serial connecting form of two stage digital filter instead of signal filter of MMA adaptive equalizer without applying the variable step size for compensates the intersymbol interference by channel distortion in the nonconstant modulus signal. The adaptive equalizer can be implemented by signal digital filter using the finite order tap delay line. In this paper, the equalizer is implemented by the two stage serial form and the filter coefficient are updated by the error signal using the same algorithm of MMA in each stage. The fast convergence speed is determined in the first stage, and the residual isi left at the output of first stage output is minimized in the second stage filter. The same digital filter length was considered in single stage and two stage system and the performance of these systems were compared. The performance index includes the output signal constellation, the residual isi and maximum distortion, MSE that is measure of the convergence characteristics, the SER. As a result of computer simulation, mMMA that has a FIR structure of two stage, has more good performance in every performance index except the constellation diagram due to equalization noise and improves the convergence speed about 1.5~1.8 time than the present MMA that has a FIR structure of single stage.

• Journal of the Institute of Convergence Signal Processing
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• v.14 no.4
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• pp.249-254
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• 2013

A fast multiplier and ADC are essential to process the analog signals in real time. The double-base number system(DBNS) is known as an efficient method for this purpose. The DBNS uses the numbers 2 and 3 as the base numbers simultaneously. The system has an advantage of fast multiplication, less chip area, and low power consumption compared to the binary multiplier. However, the inherent errors of the log number's intrinsic tolerance in DBNS are accumulated in a FIR digital filter, so the signal-to-noise ratio(SNR) has a tendency to be degraded. In this paper, the nonlinear encoder of ADC is designed to compensate the accumulated errors of DBNS by analysing the error distributions of various filter coefficients. The new ADC does not sacrifice its own advantages because the encoder circuits are modified only. The experiments were done with an FIR filters those were designed to have -70dB of SNR in stop band. The proposed nonlinear ADC encoder could drop the SNR to -45dB in stop band, in contrast to -35dB with the linear encoder.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.41 no.6
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• pp.195-208
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• 2004

Histogram is a very useful method on various practical aspect. With increasing importance of simple calculation method and convenience, it became the basic method in digital image processing nowadays. However, basic limit of using histogram is losing spatial position information of pixels on image. This paper reanalyzes image by presenting histogram with spatial position information(spatial histogram). Also using that result, level order recursive median filter is realized. Presented recursive median filter showed much improved results on edge maintenance aspect compared to existing recursive median filter.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.35-42
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• 2006

In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.11
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• pp.2039-2044
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• 2008

The problem of an efficient hardware implementation of multiple constant multiplication is frequently encountered in many digital signal processing applications such as FIR filter and linear transform (e.g., DCT and FFT). It is known that efficient solutions based on common subexpression elimination (CSE) algorithm can yield significant improvements with respect to the area and power consumption. In this paper, we present an efficient specialized adder design method for two common subexpressions ($10{\bar{1}}$, 101) in canonic signed digit (CSD) coefficients. By Synopsys simulations of a radix-24 FFT example, it is shown that the proposed method leads to about 21%, 11% and 12% reduction in the area, propagation delay time and power consumption compared with the conventional methods, respectively.

• Proceedings of the KIEE Conference
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• 1998.11a
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• pp.208-210
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• 1998

A high speed digital distance relaying algorithm based on a modified least square error method is proposed. To obtain stable phasor values very Quickly, first, a lowpass filter which has very short transient period and no overshoot is used. Secondly, the conventional least square error method is modified to the one having the data window of 3 samples by applying a FIR filter which removes the DC-offset component in current relaying signals.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.585-591
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• 2000

The wavelet transform is the most recent technique for processing signals with time-varying spectra. In this paper, the wavelet transform is utilized to improved the assessment and multi-resolution analysis of acoustic emission signals generating in partial discharge. This paper especially deals with the assessment of process statistical parameter using the features extracted from the wavelet coefficients of measured acoustic emission signals in case of applied voltage 20[kv]. Since the parameter assessment using all wavelet coefficients will often turn out leads to inefficient or inaccurate results, we selected that level-3 stage of multi decomposition in discrete wavelet transform. We applied FIR(Finite Impulse Response)digital filter algorithm in discrete to suppression for random noise. The white noise be included high frequency component denoised as decomposition of discrete wavelet transform level-3. We make use of the feature extraction parameter namely, maximum value of acoustic emission signal, average value, dispersion, skewness, kurtosis, etc. The effectiveness of this new method has been verified on ability a diagnosis transformer go through feature extraction in stage of acting(the early period, the last period) .

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.1-9
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• 1989

This paper deals with the simplification and the conversion time reduction for the 12-channel TDM/FDM transmultiplexing system using the polyphase network and the FDCT. The prototype filter required in the digital polyphase network is designed based on interpolated FIR (IFIR) properites of the IFIR coefficients, the multiplication rate required in its implementaion is shown to be $0.1640{\times}10^6$ multiplications/sec. channel which reduces about 25% of the result obtained in the previous work. The result of computer simulation indicates that the proposed conversion method is valid.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.12B
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• pp.2052-2059
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• 2000

Digital IF(Intermediate Frequency) 처리단과 같은 고속과 저전력을 요구하는 필터에서 덧셈기만을 사용하여 CSD(Canonical Signed Digit)형의 필터계수들을 구현하는 구조가 널리 연구되고 있다. 본 논문에서는 선형위상 FIR(Finite Impulse Response) 필터의 CSD형 필터계수들을 최소의 덧셈으로 구현할 수 있는 아키텍처를 제안한다. 1과 -1로 이루어진 필터계수 표에서 공통패턴을 공유함으로서 덧셈의 수를 줄이는 방법이 이미 연구되었다. 본 논문은 비트 shift, 비트 add, 비트 반전을 통하여 인공의 공통패턴을 만들어서 이미 존재하는 공통패턴에 합류시킴으로서 덧셈의 수를 더욱 줄일 수 있는 방법을 제안한다. CDMA 이동통신 단말기의 IF단에 사용되는 사양의 디지털 필터를 73탭의 CSD형 계수로 구현하여 9.2%의 덧셈 감소의 효과가 있음을 보였다.