• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.2
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• pp.14-19
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• 2011

We have fabricated GaN Schottky barrier diode (SBD) for high-voltage applications on Si substrate. The leakage current and the electrical characteristics of GaN SBD are investigated by annealing metal-semiconductor junctions. Ohmic junctions of Ti/Al/Mo/Au and Schottky junctions of Ni/Au are used in the fabrication. A test structure is proposed to measured buffer leakage current through a mesa structure. When annealing temperature is increased from $700^{\circ}C$ to $800^{\circ}C$, measured buffer leakage current is also increased from 87 nA to 780 nA at the width of 100 ${\mu}m$. The diffusion of Au, Ti, Mo, O into GaN buffer layer increases the leakage current and that is verified by Auger electron spectroscopy. Experimental results show that the low leakage current and the high breakdown voltage of GaN SBD are achieved by annealing metal-semiconductor junctions.

• Journal of the Microelectronics and Packaging Society
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• v.29 no.2
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• pp.81-89
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• 2022

The in-situ electromigration(EM) and annealing test were performed at 110, 130, and 150℃ with a current density of 1.3×10⁵ A/cm² conditions to investigate the effect of non-conductive film (NCF) on growth kinetics of intermetallic compound (IMC) in Cu/Ni/Sn-2.5Ag microbump. As a result, the activation energy of the Ni₃Sn₄ IMC growth in the annealing and EM conditions according to the NCF application was about 0.52 eV, and there was no significant difference. This is because the growth rate of Ni-Sn IMC is much slower than that of Cu-Sn IMC, and the growth behavior of Ni-Sn IMC increases linearly with the square root of time, so it has the same reaction mechanism dominated by diffusion. In addition, there is no difference in the activation energy of the Ni₃Sn₄ IMC growth because the EM resistance effect of the back stress according to the NCF application is not large.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.7
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• pp.521-524
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• 1999

Nb silicide was formed on the Si micro-tip arrays in order to improve field emission properties of Si-tip field emitter array. After silicidization of the tips, the etch-back process, by which gate insulator, gate electrode and photoresist were deposited sequentially and gate holes were defined by removing gradually the photoresist by $O_2$ plasma from the surface, was applied. Si nitride film was used as a protective layer in order to prevent oxygen from diffusion into Nb silicide layer and it was identified that the NbSi2 was formed through annealing in $N_2$ ambient at $1100^{\circ}C$ for 1 hour. By the Nb silicide coating on Si tips, the turn-on voltage was decreased from 52.1 V to 32.3 V and average current fluctuation for 1 hour was also reduced from 5% to 2%. Also, the fabricated Nb silicide-coated Si tip FEA emitted electrons toward the phosphor and light emission was obtained at the gate voltage of 40~50 V.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.100-103
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• 2001

In this study, the adhesion and thermal property of the electroless-deposited Cu thin film were investigated. The multilayered structure of Cu/TaN/Si was fabricated by electroless-depositing the Cu thin layer on the TaN diffusion barrier which was deposited by MOCVD on the Si substrate. The thermal stability was investigated by measuring the resistivity as post-annealing temperature far the multilayered Cu/TaN/Si specimen which was annealed at Ar gas. The adhesion property of Cu 171ms was evaluated by the scratch test. The adhesion of the electroless-deposited Cu film was compared with other deposition methods of thermal evaporation and sputtering. The scratch test showed that the adhesion of electroless plated Cu film on TaN was better than those of sputtered Cu film and evaporated Cu film.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.162-162
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• 2016

We present multifunctional indium tin oxide (ITO) thin films formed at room temperature by a normal sputtering system equipped with a plasma limiter which effectively blocks the bombardment of energetic negative oxygen ions (NOIs). The ITO thin film possesses not only low resistivity but also high gas diffusion barrier properties even though it is deposited on a plastic substrate at room temperature without post annealing. Argon neutrals incident to substrates in the sputtering have an optimal energy window from 20 to 30 eV under the condition of blocking energetic NOIs to form ITO nano-crystalline structure. The effect of blocking energetic NOIs and argon neutrals with optimal energy make the resistivity decrease to $3.61{\times}10-4{\Omega}cm$ and the water vapor transmission rate (WVTR) of 100 nm thick ITO film drop to $3.9{\times}10-3g/(m2day)$ under environmental conditions of 90% relative humidity and 50oC, which corresponds to a value of ~ 10-5 g/(m2day) at room temperature and air conditions. The multifunctional ITO thin films with low resistivity and low gas permeability will be highly valuable for plastic electronics applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.418-418
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• 2009

Vertically aligned arrays of multi-walled carbon nanotube (MWCNT) on layered Si substrates have been synthesized by water-assisted thermal chemical vapor deposition (CVD). We studied changes in growth by parameters of growth temperature, growth time, rates of gas and annealing time of catalyst. Also, We grew CNTs by adding a little amount of water vapor to enhance the growth of CNTs. $H_2$, Ar, and $C_2H_2$ were used as carrier gas and feedstock, respectively. Before growth, Fe served as catalyst, underneath which AI were coated as an underlayer and a diffusion barrier, respectively, on the Si substrate. The water vapor had a greater effect on the growth of CNTs on a smaller thickness of catalyst. When the water vapor was introduced, the growth of CNTs was enhanced than without water. CNTs grew 1.29 mm for 10 min long by adding the water vapor, while CNTs were 0.73 mm long without water vapor for the same period of time. CNTs grew up to 1.97 mm for 30 min prior to growth termination under adding water vapor. As-grown CNTs were characterized by using scanning electron microscopy (SEM), high resolution transmission electron microscopy (HRTEM), and Raman spectroscopy.

• Korean Journal of Materials Research
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• v.6 no.5
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• pp.483-488
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• 1996

InP 기판위에 InP와 격자정합된 undoped-InGaAs에서 zine의 확산 특성을 Electrochemical Capacitance-Voltage 법(polaron)과 Secondary Ion Mass Spectrometry(SIMS)로 조사하였다. Metallorganic Chemical Vapor Deposition (MOCVD)를 이용하여 undoped-InGaAs 층을 성장시켰으며 확산방법으로는 Zn3P2 확산원 박막과 Rapid Thermal Annealing (RTA)를 이용하였다. 450-55$0^{\circ}C$온도범위에서 30-300초 동안 확산을 수행한 결과 zinc의 확산계수는 D=Doexp(-$\Delta$E/kT)의 특성을 만족하였으며, Do와 $\Delta$E는 각각 1.3x105$\textrm{cm}^2$/sec와 2.3eV였다. 얻어진 확산계수는 다른 확산방법을 이용한 값들에 비해 매우 큰 값인데, 이것은 RTA 처리시 빠른 온도 증가에 의한 확산원 박막, 보호막, 그리고 InGaAs 에피층이 가지는 열팽창계수의 차이로인한 응력의 효과에 의한 것으로 생각되며, 이를 sealed-ampoule 법을 사용한 경우의 확산특성과 비교를 통하여 확인할 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.500-500
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• 2013

특정한 유기 물질에 전류를 인가했을 때 발광을 하는 특성을 이용한 Organic Light Emitting Diode (OLED)는 뛰어난 색재현성, 적은 전력소모, 간단한 제조공정, 넓은 시야각 등으로 인해 PDP, LCD, LED에 이은 차세대 디스플레이 소자로 많은 관심을 받고 있다. 하지만 OLED는 각기 다른 굴절률을 가지는 다층구조로 되어있어 실질적으로 소자 밖으로 나오는 빛은 원래 생성된 빛의 20% 정도 밖에 되지 않는다. 이러한 광 손실을 줄이기 위해 Photonic Crystal (PC)이나 마이크로 렌즈 어레이(MLA) 부착 등과 같이 특정한 크기를 갖는 주기적인 나노 구조물을 이용한 광추출 효율 상승 방법은 특정 파장의 빛에서만 효과가 있는 한계가 있었으며 고가의 공정과정을 거쳐야 했으므로 OLED 소자의 가격 향상에 일조하였다. 이의 해결을 위해 본 연구는 유리기판 위에 랜덤한 분포를 가지는 나노 구조물 제작 공정법을 제안한다. 먼저 유리기판 위에 스퍼터로 금속 박막을 입혀 이를 Rapid thermal annealing (RTA) 공정을 이용하여 랜덤한 분포의 Island를 가지는 마스크를 제작하였다. 그 후 플라즈마 식각을 이용하여 유리기판에 나노 구조물을 형성하였고 기판 위에 남아있는 마스크는 Ultrasonic cleaning을 이용하여 제거하였다. 제작된나노구조물은 200~300 nm의 높이와 약 200 nm 폭을 가지고 있다. 제작된 유리기판의 OLED 소자로의 적용가능성을 알아보기 위한 광학특성 조사결과는 300~900 nm의 파장영역에서 맨유리와 거의 비슷한 수직 투과율을 보이면서 최대 50%정도의 Diffusion 비율을 나타내고 있고 임계각(41도) 이상의각도에서 인가된 빛의 투과율에 대해서도 향상된 결과를 보여주고 있다. 제안된 공정의 전체과정 기존의 PC, MLA 등의 공정에 비해 난이도가 쉽고 저가로 진행이 가능하며 추후 OLED 소자에 적용될 시 대량생산에 적합한 후보로 보고 있다.

• Korean Journal of Materials Research
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• v.16 no.9
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• pp.571-577
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• 2006

We fabricated thermal evaporated 10 nm-Ni/(poly)Si and 10 nm-Ni/1 nm-Ir/(poly)Si films to investigate the thermal stability of nickel monosilicide at the elevated temperatures by rapid annealing them at the temperatures of $300{\sim}1200^{\circ}C$ for 40 seconds. Silicides for salicide process was formed on top of both the single crystal silicon actives and the polycrystalline silicon gates. A four-point tester is used for sheet resistance. Scanning electron microscope and field ion beam were employed for thickness and microstructure evolution characterization. An x-ray diffractometer and an auger depth profile scope were used for phase and composition analysis, respectively. Nickel silicides with iridium on single crystal silicon actives and polycrystalline silicon gates showed low resistance up to $1200^{\circ}C$ and $800^{\circ}C$, respectively, while the conventional nickel monosilicide showed low resistance below $700^{\circ}C$. The grain boundary diffusion and agglomeration of silicides led to lower the NiSi stable temperature with polycrystalline silicon substrates. Our result implies that our newly proposed Ir added NiSi process may widen the thermal process window for nano CMOS process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.288-291
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• 2002

Application of metal silicides such as TiSi$_2$ and CoSi$_2$ as contacts and gate electrodes are being studied. However, TiSi$_2$ due to the linewidth-dependance, and CoSi$_2$ due to the excessive Si consumption during silicidation cannot be applied to the deep-submicron MOSFET device. NiSi shows no such problems and can be formed at the low temperature. But, NiSi shows thermal instability. In this investigation, NiSi was formed with a Ti-capping layer to improve the thermal stability. Ni and Ti films were deposited by the thermal evaporator. The samples were then annealed in the N$_2$ ambient at 300-800$^{\circ}C$ in a RTA (rapid thermal annealing) system. Four point probe, FESEM, and AES were used to study the thermal properties of Ti-capped NiSi layers. The Ti-capped NiSi was stable up to 700$^{\circ}C$ for 100 sec. RTA, while the uncapped NiSi layers showed high sheet resistance after 600$^{\circ}C$. The AES results revealed that the Ni diffusion further into the Si substrate was retarded by the capping layer, resulting in the suppression of agglomeration of NiSi films.