• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.309-313
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• 2006

We demonstrated 2.2inch qqVGA AMOLED display drived by ultra low temperature poly-Si (ULTPS) TFT not transferred but direct fabricated below $200^{\circ}C$. Si channel was crystallized by decreasing impurity concentration even at room temperature. Gate insulator with a breakdown field exceeding 8 MV/cm was realized by Inductively coupled plasma - CVD. In order to reduce stress of plastic, organic film was coated as inter-dielectric and passivation layers. Finally, ULTPS TFT of which mobility is over $20cm^2/Vsec$ was fabricated on transparent plastic substrate and drived OLED display successfully.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1301-1305
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• 2005

The performance of OTFT with $PVP-TiO_2$ composite, as a gate insulator, is reported, including the effect of surfactant for synthesizing the composite material. According to our investigation results, it was one of critical issues to prevent the aggregation of $PVP-TiO_2$ particles during the synthesis process. From this point of view, $PVP-TiO_2$ particles were treated using Tween80, as a surfactant, and we could reduce the aggregated $PVP-TiO_2$ clusters. As a result, the OTFT with the composite insulator showed the threshold voltage of about -8.3 V and the subthreshold slope of about 1.5 V/decade, which are the optimized properties compared to those of OTFTs with bare PVP, in this study. It is thought that these characteristic improvements are originated from the increase in the dielectric constant of the PVP-based insulator by compositing with high-k particles.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.12
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• pp.1283-1288
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• 2004

Metal-ferroelectric-insulator-semiconductor(WFIS) capacitors using rapid thermal annealed LiNbO$_3$/AlN/Si(100) structure were fabricated and demonstrated nonvolatile memory operations. The capacitors on highly doped Si wafer showed hysteresis behavior like a butterfly shape due to the ferroelectric nature of the LiNbO$_3$ films. The typical dielectric constant value of LiNbO$_3$ film in the MFIS device was about 27, The gate leakage current density of the MFIS capacitor was 10$^{-9}$ A/cm$^2$ order at the electric field of 500 kV/cm. The typical measured remnant polarization(2P$_{r}$) and coercive filed(Ec) values were about 1.2 $\mu$C/cm$^2$ and 120 kV/cm, respectively The ferroelectric capacitors showed no polarization degradation up to 10$^{11}$ switching cycles when subjected to symmetric bipolar voltage pulses of 1 MHz. The switching charges degraded only by 10 % of their initial values after 4 days at room temperature.e.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.327-330
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• 2000

The scanning Maxwell-stress microscopy (SMM) is a dynamic noncontact electric force microscopy that allows simultaneous access to the electrical properties of molecular system such as surface potential, surface charge, dielectric constant and conductivity along with the topography. The Scanning near-field optical / atomic force microscopy (SNOAM) is a new tool for surface imaging which was introduced as one application of the atomic force microscope (AFM). Operated with non-contact forces between the optical fiber and sample as well as equipped with the piezoscanners, the instrument reports on surface topology without damaging or modifying the surface for measuring of optical characteristic in the films. We report our recent results of its application to nanoscopic study of domain structures and electrical functionality in organic thin films by SMM. Furthermore, we have illustrated the SNOAM image in obtaining the merocyanine dye films as well as the optical image.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.57-60
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• 2002

In this paper, transmission lines with low and high characteristic impedance (Z$_{0}$) are fabricated and analyzed. The transmission lines are fabricated on the benzo-cyclo-butene (BCB) films of a low dielectric constant. For the low Z$_{0}$, two types of coplanar waveguide (CPW) structures are fabricated, which include bottom-ground and double-ground type. Measurement shows that Z$_{0}$ values for each CPW type are 7.3 and 9.4$\Omega$, respectively, at a signal line width of 100 #m. Whit the ratio between the spacing of bottom-ground and the signal line with becomes greater than 2.5, the Z$_{0}$ is nearly saturated. In addition, thin film microstrip lines fabricated using the BCB insertion layers show very low Z$_{0}$ of 25.5$\Omega$, and this impedance is ~64 % of the values obtained from the BCB-based CPW structures of the same line width. Measurement result of CPW on BCB layer is 100.5 Ω.s 100.5 Ω.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.1 s.38
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• pp.17-22
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• 2006

Ferroelectric PZT thin films were formed by 2-step sputtering and their dielectric properties and conduction mechanisms were investigated. Also. donor impurity doping was tried to compensate the carriers in PZT thin films. The leakage current density was able to reduce to $10^{-7}A/cm^2$ order by 2-step sputtering with thickness control of room temp.-layer. The conduction mechanism was confirmed as bulk-limited, and optimum donor impurities on PZT thin film were taken. Especially, leakage current characteristics was improved to $10^{-8}A/cm^2$ order in donor-doped PZT thin films formed by 2-step sputtering.

• Journal of the Microelectronics and Packaging Society
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• v.12 no.4 s.37
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• pp.345-349
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• 2005

Low resistive ($300{\mu}{\Omega}$-cm) W-C-N films have been deposited on tetraethylorthosilicate (TEOS) interlayer dielectric by atomic layer deposition (ALD) with $WF_6-N_2-CH_4$ gas. The exposure cycles of $N_2$ and $CH_4$ are synchronized with pulse plasma. The W-C-N films on TEOS layer follow the ALD mechanism and keep constant deposition rate of 0.2 nm/cycle from 10 to 100 cycles. As a diffusion barrier for Cu interconnection the W-C-N films maintain amorphous phase and Cu inter-diffusion is not occurred even at $800^{\circ}C$ for 30 min.

• Journal of the Institute of Electronics Engineers of Korea TE
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• v.42 no.4
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• pp.1-6
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• 2005

Recently embedded passive technology which fabricate passive elements such as resistors and capacitors at the inner layer of PCB(Printed Circuit Board) is used to make high performance IT products. However, embedded capacitor has limit in full range circuit applications because of the low capacitance density. In this paper, a new embedded capacitor which has wrinkled electrodes and dielectric layer was proposed to overcome the limits. FEM(Finite Elements Method) technique was used to evaluate capacitance density of the wrinkled type embedded capacitor. Capacitance density of the wrinkled type embedded capacitor is larger than that of conventional planar type embedded capacitor by about 25.6%$\sim$39.6%. In case of thin film type embedded capacitor, proposed wrinkled structure has more enhanced effect on the capacitance density.

• Progress in Superconductivity and Cryogenics
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• v.4 no.1
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• pp.30-34
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• 2002

In this Paper, Insulation of current lead in the conduction-cooled DC reactor for the 1.2kV class 3 high-Tc superconducting fault current limiter(SFCL) is studied. Thermal link which conducts heat energy but insulates electrical energy is selected as a insulating device for the current lead in the conduction-cooled Superconducting DC reactor. It consists of oxide free copper(OFC) sheets, Polyimide films, glass fiberglass reinforced Plastics (GFRP) plates and interfacing material such an indium or thermal compound. Through the test of dielectric strength in L$N_2$, polyimide film thickness of 125 ${\mu}{\textrm}{m}$ is selected as a insulating material. Electrical insulation and heat conduction are contrary to each other. Because of low heat conductivity of insulator and contact area between electrical insulator and heat conductor, thermal resistance of conduction-cooled system is increased. For the reducing of thermal resistance and the reliable contact between Polyimide and OFC, thermal compound or indium can be used As thermal compound layer is weak layer in electrical field, indium is finally selected for the reducing of thermal resistance. Thermal link is successfully passed the test. The testing voltage was AC 2.5kVrms and the testing time was 1 hour.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1992.11a
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• pp.90-93
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• 1992

In this paper, MOS characteristics of gate dielectrics prepared by furnace oxidation of Si in an $N_2O$ ambient have been studied. Compared with the oxides grown in $O_2$, $N_2O$ oxides show significantly improved breakdown field and low flat band voltage. Also, $N_2O$ oxide is more controllable for ultrathin film growth than $O_2$ oxide. This improvement is caused by nitrogen incorporation into the $N_2O$ oxide. Therefore, the nitrogen-rich-layer at the Si/$SiO_2$ interface formed during $N_2O$ oxidation not only strengthen $N_2O$ oxide structure at the interface and improves the gate dielectric quality, it also acts as a oxidant diffusion barrier that reduces the oxidation rate significantly.