• Title/Summary/Keyword: device degradation

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Evaluation Method for Communication Distance Measurement Method for Mobility Characteristics of Service Robot in Wi-Fi Network Based (Wi-Fi 네트워크 기반에서 서비스 로봇의 이동특성을 위한 통신거리 성능평가 방법)

  • Min, Sun-Ho;Seo, Chang-Ho;Hong, Do-Won
    • Journal of Digital Convergence
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    • v.10 no.3
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    • pp.265-271
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    • 2012
  • This paper proposes a communication distance performance evaluation method for mobility of service robots equipped with a Wi-Fi module. Service robots have function of mobile communication system according to classified services and utilize a (preferred) communication method, wireless lan(IEEE802.11 a/b/gin) communication method of ISM band(2.4GHz and 5.8GHz). For evaluating degradation performance of wireless data for the service robot's mobility. We measured and presented reference vectors obtained by utilizing a distance attenuation correlation method in the real world environment. To evaluate performance of the proposed method, path loss of reference vectors was assigned to the Azimuth 301W and then transmission rate and the transmit throughput of the test sample were measured by the Chariot. The proposed measurement method is necessary for securing wireless LAN communication distance for mobility of mobile smart device and service robots. In addition, if the proposed measurement method os adopted, It would be expected that mobile smart device vendors would utilize the method as an effective wireless LAN mobility communication distance performance evaluation method.

A Subthreshold Slope and Low-frequency Noise Characteristics in Charge Trap Flash Memories with Gate-All-Around and Planar Structure

  • Lee, Myoung-Sun;Joe, Sung-Min;Yun, Jang-Gn;Shin, Hyung-Cheol;Park, Byung-Gook;Park, Sang-Sik;Lee, Jong-Ho
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.3
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    • pp.360-369
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    • 2012
  • The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

Development of virtio Network Driver for RTEMS Open-Source Operating System (RTEMS 오픈소스 운영체제를 위한 virtio 네트워크 드라이버 개발)

  • Kim, Jin-Hyun;Jin, Hyun-Wook
    • KIISE Transactions on Computing Practices
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    • v.23 no.4
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    • pp.262-267
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    • 2017
  • RTEMS is a real-time operating system using a GPLv2-based license, and is used in the aerospace industry, such as satellites. It is difficult to build a development environment for these special-purpose systems because of problems related to the hardware platform. This can be resolved by applying virtualization technology. However, increased execution time and performance degradation due to virtualization overhead can change timing behavior of real-time application, and needs to be minimized. In this paper, we aim to implement the network device driver of RTEMS for the standardized virtual network device called virtio in order to effectively utilize RTEMS in a virtualized environment. In addition, we describe the process of submitting implemented driver to the RTEMS community for contributing open source software and reflecting the various requirements of the community.

A Study on the Development of PD Simulation Pulse Generator for Evaluation of GIS Diagnosis System (GIS 진단시스템의 평가를 위한 PD 모의 펄스발생기 개발에 관한 연구)

  • Kim, Sungju;Chang, Sughun;Cho, Kook-hee
    • Journal of the Korean Society of Safety
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    • v.33 no.2
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    • pp.21-27
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    • 2018
  • The expansion and stable operation of electric power facilities are important factors with development of industrial facilities in modern society. In high-voltage equipment such as GIS, the insulation characteristics may be deterioated by environment-friendly gas adaption and miniaturization. There is also the possibility of accidents due to insulation breakdown due to the deterioration of power facilities. Therefore, it is necessary to extend the diagnosis system to continuously monitor the danger signals of these power equipment and to prevent accidents. Most of the internal defects in the GIS system are conductive particles, floating electrode defects, protrusion defects, and the like. In this case, a partial discharge phenomenon is accompanied. These partial discharge signals occur irregularly and various noise signals are included in the field, so it is difficult to evaluate the reliability in the development of the diagnostic system. In this paper, a study was made on equipment capable of generating a partial discharge simulated signal that can be adjusted in size and frequency to be applied to a diagnostic device by electromagnetic wave detection method. The PD simulated pulse generator consists of a user interface module, a high-voltage charging module, a pulse forming circuit, a voltage sensor and an embedded controller. In order to simulate the partial discharge phenomenon similar to the actual GIS, a discharge cell was designed and fabricated. The application of the prototype pulse generator to the commercialized PD diagnosis module confirmed that it can be used to evaluate the performance of the diagnostic device. It can be used for the development of GIS diagnosis system and performance verification for reliability evaluation.

Garbage Collection Synchronization Technique for Improving Tail Latency of Cloud Databases (클라우드 데이터베이스에서의 꼬리응답시간 감소를 위한 가비지 컬렉션 동기화 기법)

  • Han, Seungwook;Hahn, Sangwook Shane;Kim, Jihong
    • Journal of KIISE
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    • v.44 no.8
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    • pp.767-773
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    • 2017
  • In a distributed system environment, such as a cloud database, the tail latency needs to be kept short to ensure uniform quality of service. In this paper, through experiments on a Cassandra database, we show that long tail latency is caused by a lack of memory space because the database cannot receive any request until free space is reclaimed by writing the buffered data to the storage device. We observed that, since the performance of the storage device determines the amount of time required for writing the buffered data, the performance degradation of Solid State Drive (SSD) due to garbage collection results in a longer tail latency. We propose a garbage collection synchronization technique, called SyncGC, that simultaneously performs garbage collection in the java virtual machine and in the garbage collection in SSD concurrently, thus hiding garbage collection overheads in the SSD. Our evaluations on real SSDs show that SyncGC reduces the tail latency of $99.9^{th}$ and, $99.9^{th}-percentile$ by 31% and 36%, respectively.

Characteristics of Ta-Ti Gate Electrode for NMOS Device (NMOS 소자의 Ta-Ti 게이트 전극 특성)

  • Kang, Young-Sub;Seo, Hyun-Sang;Noh, Young-Gin;Lee, Chung-Keun;Hong, Shin-Nam
    • Journal of Advanced Navigation Technology
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    • v.7 no.2
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    • pp.211-216
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    • 2003
  • In this paper, characteristics of Ta-Ti alloy was studied as a gate electrode for NMOS devices to replace the widely used polysilicon. Ta-Ti alloy was deposited directly on $SiO_2$ by a co-sputtering method using two of Ta and Ti targets. The sputtering power of each metal target was 100W. To compare with Ta-Ti, Ta deposited with a 100W sputtering power was fabricated as well. In order to investigate the thermal/chemical stability of the Ta-Ti alloy gate, the alloy was annealed at $600^{\circ}C$ with rapid thermal annealer. No appreciable degradation of the device was observed. Also the results of electrical analysis showed that the work function of Ta-Ti metal alloy was about 4.1eV which was suitable for NMOS devices and sheet resistance of alloy was lower than that of polysilicon.

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Deuterium Ion Implantation for The Suppression of Defect Generation in Gate Oxide of MOSFET (MOSFET 게이트 산화막내 결함 생성 억제를 위한 효과적인 중수소 이온 주입)

  • Lee, Jae-Sung;Do, Seung-Woo;Lee, Yong-Hyun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.7
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    • pp.23-31
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    • 2008
  • Experiment results are presented for gate oxide degradation under the constant voltage stress conditions using MOSFETs with 3-nm-thick gate oxides that are treated by deuterium gas. Two kinds of methods, annealing and implantation, are suggested for the effective deuterium incorporation. Annealing process was rather difficult to control the concentration of deuterium. Because the excess deuterium in gate oxide could be a precursor for the wear-out of gate oxide film, we found annealing process did not show improved characteristics in device reliability, compared to conventional process. However, deuterium implantation at the back-end process was effective method for the deuterated gate oxide. Device parameter variations as well as the gate leakage current depend on the deuterium concentration and are improved by low-energy deuterium implantation, compared to those of conventional process. Especially, we found that PMOSFET experienced the high voltage stress shows a giant isotope effect. This is likely because the reaction between "hot" hole and deuterium is involved in the generation of oxide trap.

Cu Metallization for Giga Level Devices Using Electrodeposition (전해 도금을 이용한 기가급 소자용 구리배선 공정)

  • Kim, Soo-Kil;Kang, Min-Cheol;Koo, Hyo-Chol;Cho, Sung-Ki;Kim, Jae-Jeong;Yeo, Jong-Kee
    • Journal of the Korean Electrochemical Society
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    • v.10 no.2
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    • pp.94-103
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    • 2007
  • The transition of interconnection metal from aluminum alloy to copper has been introduced to meet the requirements of high speed, ultra-large scale integration, and high reliability of the semiconductor device. Since copper, which has low electrical resistivity and high resistance to degradation, has different electrical and material characteristics compared to aluminum alloy, new related materials and processes are needed to successfully fabricate the copper interconnection. In this review, some important factors of multilevel copper damascene process have been surveyed such as diffusion barrier, seed layer, organic additives for bottom-up electro/electroless deposition, chemical mechanical polishing, and capping layer to introduce the related issues and recent research trends on them.

An Analysis of the Radio Interference in Wireless Vehicular Networks based on IEEE802.11b(WLAN) (IEEE802.11b(WLAN)기반의 차량 무선통신환경에서 전파간섭분석)

  • Lee, Myungsub;Park, Changhyeon
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.12 no.6
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    • pp.117-125
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    • 2012
  • Recently, there has been a fast paradigm shift in the automotive market from the traditional machine-oriented technology into the technology for vehicle informatics and electronics. In particular, telematics market is accelerating the development of technologies for vehicle informatics through the close cooperation between the vehicle makers and mobile communication companies. However, there may be the degradation of the quality of service by the interference since the telematics uses the wireless communication infrastructure for the base station-to-vehicle communication and the vehicle-to-vehicle communication. This paper presents an analysis device to easily analyze the interference by the wireless communication in the vehicle wireless network environment. Using the analysis results by the presented device, this paper shows that the link quality can be improved through the simulation and the experiment in real environment both.

Acceleration techniques for GPGPU-based Maximum Intensity Projection (GPGPU 환경에서 최대휘소투영 렌더링의 고속화 방법)

  • Kye, Hee-Won;Kim, Jun-Ho
    • Journal of Korea Multimedia Society
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    • v.14 no.8
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    • pp.981-991
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    • 2011
  • MIP(Maximum Intensity Projection) is a volume rendering technique which is essential for the medical imaging system. MIP rendering based on the ray casting method produces high quality images but takes a long time. Our aim is improvement of the rendering speed using GPGPU(General-purpose computing on Graphic Process Unit) technique. In this paper, we present the ray casting algorithm based on CUDA(an acronym for Compute Unified Device Architecture) which is a programming language for GPGPU and we suggest new acceleration methods for CUDA. In detail, we propose the block based space leaping which skips unnecessary regions of volume data for CUDA, the bisection method which is a fast method to find a block edge, and the initial value estimation method which improves the probability of space leaping. Due to the proposed methods, we noticeably improve the rendering speed without image quality degradation.