• 전자공학회논문지
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• 제53권1호
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• pp.51-58
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• 2016

반도체 제조공정의 발달로 칩의 성능은 더욱 향상되었으나 회로가 미세해지고 복잡해져 동작 환경에 의한 회로의 노화가 가속화 될 수 있다. 회로의 노화는 성능 저하로 나타나며, 결과적으로 시스템 오류를 발생 시킬 수 있다. 고신뢰 시스템에서는, 노화로 인한 오류가 큰 재난으로 이어질 수 있으므로, 사고를 예방하기 위한 오류 발생 예측 기술이 필수적이다. 본 논문에서는 회로의 정상동작 중에 성능 저하를 감지하여 오류를 예측 할 수 있는 모니터링 기법을 제시한다. 모니터링을 위한 별도의 회로를 추가하지 않고 경계 스캔 셀과 TAP 제어기를 재활용한 IEEE 1149.1 경계 스캔 기반의 온-라인 성능 저하 모니터링 방법을 제시한다. 시뮬레이션을 통하여 제안하는 성능 저하 모니터링 기법을 검증한다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2003년도 International Meeting on Information Display
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• pp.21-24
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• 2003

The understanding of the mechanism of device degradation has been accomplished recently, for devices using $AlQ_3$ electron transport and emitter molecule. In this presentation the experimental evidence for the degradation mechanism of $AlQ_3$ based devices will be reviewed, showing that the hypothesis of an unstable $AlQ_3^+$ cation explains a large amount of experimental data. This hypothesis, however, explains not only the room temperature device degradation in time but also sheds light on temperature stability of OLEDs. Dependence of half-life of a series of devices with an emitter layer composed of a mixture of $AlQ_3$ and different hole transport molecules (mixed emitter layer) will be discussed when they are operated at elevated temperatures. These results can also be explained in the framework of an unstable $AlQ_3^+$ species. An OLED structure containing a doped mixed emitter layer will be described, which shows extraordinary stability, half-life of 1200 hours at operating temperature of 70 C and initial luminance of 1650 $cd/m^2$. We will also discuss a novel Black $Cathode^{TM}$ OLED with reduced optical reflectivity, which is also stable at elevated temperatures. The new cathode utilizes a conductive light-absorbing layer made of a mixture of metals and organic materials.

• 한국복합재료학회:학술대회논문집
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• 한국복합재료학회 2004년도 추계학술발표대회 논문집
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• pp.286-289
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• 2004

This paper presents the fatigue characteristics of LIPCA (LIghtweight Piezo-Composite Actuator) device system. The LIPCA device system is composed of a piezoelectric ceramic layer and fiber reinforced lightweight composite layers. Typically a PZT ceramic layer is sandwiched by a top fiber layer with low CTE (coefficient of thermal expansion) and base layers with high CTE. The advantages of the LIPCA design are weight reduction by using the lightweight fiber reinforced plastic layers without compromising the generation of high force and large displacement and design flexibility by selecting the fiber direction and the size of prepreg layers. To predict the degradation of actuation performance of LIPCA due to fatigue, the cyclic electric loading tests using PZT specimens were performed and the strain for a given excitation voltage was measured during the test. The results from the PZT fatigue test were implemented into CLPT (Classical Laminated Plate Theory) model to predict the degradation of LIPCA's actuation displacement. The fatigue characteristic of PZT was measured using a test system composed of a supporting jig, a high voltage power supplier, data acquisition board, PC, and evaluated.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1467-1469
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• 2007

We report on the effect of ambient gas on the OLED degradation. The operating voltage and quantum efficiency increases when the device is exposed to the atmospheric gas and then returns to the initial level of the device in vacuum when the atmospheric gas is evacuated. These changes in the OLED performance can be attributed to the ambient gas pressure.

• 전자공학회논문지A
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• 제32A권8호
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• pp.126-132
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• 1995

The electrical stress of short channel polycrystalline silicon (poly-Si) thin film transistor (TFT) has been investigated. The device characteristics of short channel poly-Si TFT with 5$\mu$m channel length has been observed to be significantly degraded such as a large shift in threshold voltage and asymmetric phenomena after the electrical stress. The dominant degradation mechanism in long channel poly-Si TFT's with 10$\mu$m and 20$\mu$m channel length respectively is charage trappling in gate oxide while that in short channel device with 5.mu.m channel length is defect creation in active poly-Si layer. We propose that the increased defect density within depletion region near drain junction due to high electric field which could be evidenced by kink effect, constitutes the important reason for this significant degradation in short channel poly-Si TFT. The proposed model is verified by comparing the amounts of the defect creation and the charge trapping from the strechout voltage.

• Transactions on Electrical and Electronic Materials
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• 제6권1호
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• pp.1-5
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• 2005

Continued scaling of MOS devices requires the formation of the ultra shallow and very heavily doped junction. The simulation and experiment results show that the degradation of pMOS performance in logic and SRAM pMOS devices due to the excessive diffusion of the tail and a large amount of dose loss in the extension region. This problem comes from the high-temperature long-time deposition process for forming the spacer and the presence of fluorine which diffuses quickly to the $Si/SiO_{2}$ interface with boron pairing. We have studied the method to improve the pMOS performance that includes the low-energy boron implantation, spike annealing and device structure design using TCAD simulation.

• 한국전기전자재료학회논문지
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• 제28권8호
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• pp.539-543
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• 2015

At present, the development of a detection device in order to prevent accidents due to wire deterioration in the distribution lines is required. Distribution line is not possible to check the internal state in a normal way because it is covered with the coating. Accordingly, various eddy current techniques that is the non-destructive test (NDT) techniques have been applied to solve this problem. In this paper, we have seen examining the characteristic change of the eddy current sensor according to the simplified shape of the sensor in order to solve the problems for the simplified shape that is generated when the simulation for the shape of the eddy current sensor.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 추계학술대회 논문집
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• pp.113-116
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• 1996

The drain current of the MOSFET in the off state(i.e., Id when Vgs=0V) is undesired but nevertheless important leakage current device parameter in many digital CMOS IC applications (including DRAMs, SRAMs, dynamic logic circuits, and portable systems). The standby power consumed by devices in the off state have added to the total power consumed by the IC, increasing heat dissipation problems in the chip. In this paper, hot-carrier-induced degra- dation and gate-induced-drain-leakage curr- ent under worse case in P-MOSFET\`s have been studied. First of all, the degradation of gate-induced- drain-leakage current due to electron/hole trapping and surface electric field in off state MOSFET\`s which has appeared as an additional constraint in scaling down p-MOSFET\`s. The GIDL current in p-MOSFET\`s was decreased by hot-electron stressing, because the trapped charge were decreased surface-electric-field. But the GIDL current in n-MOS77T\`s under worse case was increased.

• 한국전기전자재료학회논문지
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• 제13권2호
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• pp.101-105
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• 2000

The effects of electrical on n-channel offset gated poly-Si TFT's have been investigated. It is observed that the electrical field near the drain region in offset devices is smaller than that of conventional device by simulation results. The variation rate of threshold voltage and subthreshold slope decrease with increasing the offset length because of lowering the electric field near the drain region. The offset gated poly-Si TFT's have been probed effective in reducing the degradation rate of device performance under electrical stressing.

• Nuclear Engineering and Technology
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• 제55권11호
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• pp.4238-4245
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• 2023

In order to predict the lifetime of InP Heterojunction Bipolar Transistor (HBT) devices and related circuits in the space radiation environment, a novel model including gamma radiation effects is proposed in this paper. Based on the analysis of radiation-induced device degradation effects including both DC and AC characteristics, a set of empirical expressions describing the device degradation trend are presented and incorporated into the Keysight model. To validate the effective of the proposed model, a series of radiation experiments are performed. The correctness of the novel model is validated by comparing experimental and simulated results before and after radiation.