• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.91_92
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• 2009

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.4
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• pp.796-800
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• 2011

As the increasing integrity of VLSI, the BIST(Built-In Self Test) is used as an effective method to test chips. Generally the pseudo-random test pattern generation is used for BIST. But it requires too many test patterns when there exist random resistant faults. Therefore we propose a mixed test scheme which applies to the circuit under test, a deterministic test sequence followed by a pseudo-random one. This scheme allows the maximum fault coverage detection to be achieved, furthermore the silicon area overhead of the mixed hardware generator can be reduced.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.71-79
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• 2000

The original March algorithms cannot detect CMOS ADOFs(Address Decoder Open Faults) which requires separate deterministic test patterns. Modified March algorithm using DOF(Degree of Freedom) was suggested to detect these faults in addition to conventional stuck faults. This paper augments the modified march test to further capture NPSFs(Neighborhood Pattern Sensitive Faults). Complete CA(Cellular Automata) is used for address generation and Rl-LFSRs(Randomly Inversed LFSRs) for data generation. A new modified March algorithm can detect SAF, CF, TF, CMOS ADOFs, and part of NPSFs. Time complexity of this algorithm is still O(n).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.79-90
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• 2005

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with the conventional methods.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.3
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• pp.131-136
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• 1990

In this paper, new methods are proposed which speed up the logical redundancy identification for the gate-level logic optimization. Redundancy indentification, as well as deterministic test pattern generation, can be viewed as a finite space search problem, of which execution time depends on the size of the search space. For the purpose of efficient search, we propose dynamic head line and mandatory assignment. Dynamic head lines are changed dynamically in the process of the redundancy identification. Mandatory assignement can avoid unnecessary assignment. They can reduce the search size efficiently. Especially they can be used even though the circuit is modified in the optimization procedure, that is different from the test pattern generation methods. Some experimental results are presented indicating that the proposed methods are faster than existing methods.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2006.11a
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• pp.693-696
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• 2006

Global optimization is a method for finding more reliable models in various fields, such as financial engineering, pattern recognition, process optimization. In this study, we compare and analyze the performance of the state-of-the-art global optimization techniques, which include Genetic Algorithm (DE,SCGA), Simulated Annealing (ASA, DSSA, SAHPS), Tabu & Direct Search (DTS, DIRECT), Deterministic (MCS, SNOBIT), and Trust-Region algorithm. The test functions for the experiments are Benchmark problems in Hedar & Fukushima (2004), which are evaluated with respect to efficiency and accuracy. Through the experiment, we analyse the computational complexity of the methods and finally discuss the pros and cons of them.

• Journal of the Korea institute for structural maintenance and inspection
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• v.8 no.2
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• pp.159-167
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• 2004

The compressive strength of concrete is a criterion to produce concrete. However, the tests on the compressive strength are complicated and time-consuming. More importantly, it is too late to make improvement even if the test result does not satisfy the required strength, since the test is usually performed at the 28th day after the placement of concrete at the construction site. Therefore, strength prediction before the placement of concrete is highly desirable. This study presents the probabilistic technique for predicting the compressive strength of concrete on the basis of concrete mix proportions. The estimation of the strength is based on the probabilistic neural network which is an effective tool for pattern classification problem and gives a probabilistic result, not a deterministic value. In this study, verifications for the applicability of the probabilistic neural networks were performed using the test results of concrete compressive strength. The estimated strengths are also compared with the results of the actual compression tests. It has been found that the present methods are very efficient and reasonable in predicting the compressive strength of concrete probabilistically.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.8 s.350
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• pp.27-34
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• 2006

During Built-In Self-Test(BIST), The set of patterns generated by a pseudo-random pattern generator may not provide sufficiently high fault coverage and many patterns were undetected fault. In order to reduce the test time, we can remove useless patterns or change from them to useful patterns. In this paper, we reseed modify the pseudo-random and use an additional bit flag to improve test length and achieve high fault coverage. the fat that a random tset set contains useless patterns, so we present a technique, including both reseeding and bit modifying to remove useless patterns or change from them to useful patterns, and when the patterns change, we choose number of different less bit, leading to very short test length. the technique we present is applicable for single-stuck-at faults. the seeds we use are deterministic so 100% faults coverage can be achieve.