• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.4
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• pp.303-309
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• 2013

A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82mW with a single power supply of 1.2V and achieves 4.9 effective number of bits for input frequency up to 1MHz at 500 MS/s. Therefore it results in 4.75pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.8
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• pp.1810-1816
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• 2009

In 2007, 9,128 fires were actually caused by electrical faults and these fires resulted in 29 deaths and 262 injuries. Arc-faults were one of the major causes of these fires. When an unintended arc-fault occurs, it generates intense heat that can easily ignite surrounding combustibles. But, because conventional circuit breakers only respond to overloads, short circuits, and leakage currents, the breakers do not protect against arcing conditions. This paper presents results obtained in experiments on ignition behavior of wire by series arc fault currents and techniques developed to detect the arc-faults. The developed technique was tested after installation to make sure that they are working properly and protecting the circuit. If the developed arc fault detection technique is applied, the electrical fires caused by an arc-fault can be reduced.

• Journal of the Korea Society of Computer and Information
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• v.24 no.8
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• pp.19-28
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• 2019

In this paper, an online video summarization algorithm based on multiple object detection is proposed. As crime has been on the rise due to the recent rapid urbanization, the people's appetite for safety has been growing and the installation of surveillance cameras such as a closed-circuit television(CCTV) has been increasing in many cities. However, it takes a lot of time and labor to retrieve and analyze a huge amount of video data from numerous CCTVs. As a result, there is an increasing demand for intelligent video recognition systems that can automatically detect and summarize various events occurring on CCTVs. Video summarization is a method of generating synopsis video of a long time original video so that users can watch it in a short time. The proposed video summarization method can be divided into two stages. The object extraction step detects a specific object in the video and extracts a specific object desired by the user. The video summary step creates a final synopsis video based on the objects extracted in the previous object extraction step. While the existed methods do not consider the interaction between objects from the original video when generating the synopsis video, in the proposed method, new object clustering algorithm can effectively maintain interaction between objects in original video in synopsis video. This paper also proposed an online optimization method that can efficiently summarize the large number of objects appearing in long-time videos. Finally, Experimental results show that the performance of the proposed method is superior to that of the existing video synopsis algorithm.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.7
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• pp.42-48
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• 2016

In this paper, a high-precision peak detector circuit that detects the output voltage information of a fly-back converter is proposed. The proposed design consists of basic analog elements with only one operational amplifier and three transistors. Because of its simple structure, the proposed circuit can minimize the delay time of the detection process, which has a strong impact on the precision of the regulation aspect of the fly-back converter. Furthermore, by using an amplifier and several transistors, the proposed detector can be fully integrated on-chip, instead of using discrete circuit elements, such as capacitors and diodes, as in conventional designs, which reduces the production cost of the fly-back converter module. In order to verify the performance of the proposed scheme, the peak detector was simulated and implemented by using a 0.35 m MagnaChip process. The gained results from the simulation with a sinusoidal stimulus signal show a very small detection error in the range of 0.3~3.1%, which is much lower than other reported detecting circuits. The measured results from the fabricated chip confirm the simulation results. As a result, the proposed peak detector is recommended for designs of high-performance fly-back converters in order to improve the poor regulation aspect seen in conventional designs.

• Journal of Sensor Science and Technology
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• v.12 no.4
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• pp.191-197
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• 2003

Due to explosive increase of internet usage, broadband data transmission using optical fibers is broadly used. In order to decrease distortion during long distance transmission, the optical signal need to be restored, typically, by converting the optical signal into the electrical signal. The optical signal is converted into the electrical signal using a photo-diode, and then a clock-and-recovery (CDR) circuit is used to recover the clock and retime the data. In this study, a clock-and-data recovery circuit has been designed using a standard 1.8 V $0.18\;{\mu}m$ CMOS process. With this CDR circuit, the improved phase detector and charge pump have been utilized. Also, by using a ring oscillator, the CDR circuit can recover clock and data from broadband multi-rate data ranging between 750 Mb/s and 2.85 Gb/s.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.124-129
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• 2013

This paper proposes a high-performance vector inner product calculation circuit for real-time object recognition based on SVM algorithm. SVM algorithm shows a higher detection rate than other object recognition algorithms. However, it requires a huge amount of computational efforts. Since vector inner product calculation is one of the major operations of SVM algorithm, it is important to implement a high-performance vector inner product calculation circuit for real-time object recognition capability. The proposed circuit adopts the pipeline architecture with six stages to increase the operating speed and makes it possible to recognize objects in real time based on SVM. The proposed circuit was described in Verilog HDL at RTL. For silicon verification, an MPW chip was fabricated using TSMC 180nm standard cell library. The operation of the implemented MPW chip was verified on the test board with test application software developed for the chip verification.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.17 no.2 s.105
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• pp.129-133
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• 2006

In spite of the advantage of simple circuit, small size, and low price, predistortered power amplifier does not satisfy the IMD specification at low power range because of an IMD hump characteristic. To reduce the performance degradation by IMD hump, the method which is to control the operating point of amplifier according to its output power is presented. This method using envelope detection bias control is applied to the implemented class AB predistortered 16 W power amplifier. The measured result shows 10 dB improvement of $3^{rd}$ IMD performance in wide dynamic range of output power.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.6
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• pp.138-144
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• 2013

In XRF systems, various techniques have been developed for the synthesis of pulse shapes using digital methods instead of traditional analog methods. Trapezoidal pulse shaping algorithms can be used for digital multi-channel pulse height analysis in X-ray spectrometer systems. In this paper, an efficient trapezoidal filter architecture is presented. In addition, we present a hardware-efficient peak value detection algorithm. By the proposed algorithm, peak value detection error is decreased by half compared with the conventional algorithm. The proposed Digital Pulse Processing(DPP) algorithm is designed using Verilog HDL and implemented using an FPGA on a test board. It is demonstrated that the implemented DPP board works successfully in practical XRF systems.

• Journal of Korea Multimedia Society
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• v.20 no.3
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• pp.482-490
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• 2017

Early detection of infiltration is one of the most important tasks of nurses to minimize skin damage due to infiltration. For subjects receiving invasive intravenous treatment, the bioelectrical impedance (impedance) were measured in the frequency range of 5 to 500 kHz using bioelectrical impedance spectroscopy (BIS). After attaching electrodes at both ends of a transparent dressing mounted on the skin in which IV solution was infused into the vein, the change in impedance was measured as a function of time and frequency before and after infiltration. The experimental results are described as follows. When IV solution was properly infused into the vein, the impedance was nearly constant over time and decreased with increasing frequency. However, when infiltration occurred, the impedance decreased significantly and thereafter gradually decreased with time. In addition, impedance decreased with time for all applied frequencies. In this study, when IV solution penetrated into the surrounding skin and subcutaneous tissue by infiltration, impedance was quantitatively analyzed for as a function of time and frequency. This suggests a method for early detection of infiltration using BIS.

• The Transactions of the Korean Institute of Power Electronics
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• v.17 no.6
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• pp.546-552
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• 2012

This paper presents an active anti-islanding detection method using negative sequence voltage injection to the grid through a three-phase photovoltaic inverters. Because islanding operation mode can cause a variety of problems, the islanding detection of grid-connected photovoltaic inverter is the mandatory feature. The islanding mode is detected by measuring the magnitude of negative sequence impedance calculated by the negative sequence voltage and current at the point of common coupling. Simulation and experimental test are performed to verify the effectiveness of the proposed method which can detect the islanding mode in the specified time. The test has been done in accordance with the condition on IEEE Std 929-2000.