• 제목/요약/키워드: degradation process

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DEVS 형식론을 이용한 다중프로세서 운영체제의 모델링 및 성능평가

  • 홍준성
    • 한국시뮬레이션학회:학술대회논문집
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    • 한국시뮬레이션학회 1994년도 추계학술발표회 및 정기총회
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    • pp.32-32
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    • 1994
  • In this example, a message passing based multicomputer system with general interdonnedtion network is considered. After multicomputer systems are developed with morm-hole routing network, topologies of interconecting network are not major considertion for process management and resource sharing. Tehre is an independeent operating system kernel oneach node. It communicates with other kernels using message passingmechanism. Based on this architecture, the problem is how mech does performance degradation will occur in the case of processor sharing on multicomputer systems. Processor sharing between application programs is veryimprotant decision on system performance. In almost cases, application programs running on massively parallel computer systems are not so much user-interactive. Thus, the main performance index is system throughput. Each application program has various communication patterns. and the sharing of processors causes serious performance degradation in hte worst case such that one processor is shared by two processes and another processes are waiting the messages from those processes. As a result, considering this problem is improtant since it gives the reason whether the system allows processor sharingor not. Input data has many parameters in this simulation . It contains the number of threads per task , communication patterns between threads, data generation and also defects in random inupt data. Many parallel aplication programs has its specific communication patterns, and there are computation and communication phases. Therefore, this phase informatin cannot be obtained random input data. If we get trace data from some real applications. we can simulate the problem more realistic . On the other hand, simualtion results will be waseteful unless sufficient trace data with varisous communication patterns is gathered. In this project , random input data are used for simulation . Only controllable data are the number of threads of each task and mapping strategy. First, each task runs independently. After that , each task shres one and more processors with other tasks. As more processors are shared , there will be performance degradation . Form this degradation rate , we can know the overhead of processor sharing . Process scheduling policy can affects the results of simulation . For process scheduling, priority queue and FIFO queue are implemented to support round-robin scheduling and priority scheduling.

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플라스틱 소재의 탈변색 열화 메커니즘 분석 (A Study for Degradation Mechanism of Plastic Materials)

  • 윤형준;정원욱;변두진;최기대
    • 한국신뢰성학회지:신뢰성응용연구
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    • 제7권4호
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    • pp.173-181
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    • 2007
  • Out door exposure to daylight and weather climate conditions can cause adverse effect on the properties of automotive plastic materials. The effects of sunlight exposure, especially ultra violet (UV) radiation, can break down the chemical bonds in a polymeric material. This degradation process is called photo-degradation and ultimately leads to color changes, cracking, chalking, the loss of physical properties and deterioration of other properties. To explore the effect of sunlight exposure on the automotive materials, this study investigated photo-oxidation degree and surface property change of molding parts by analytical methods. For the further study, accelerated weathering test methods are proposed, which can correlate with out door weathering, to predict long term performance of automotive plastic materials.

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자외선 파장에 따른 FRP의 표면 열화특성 및 열화메커니즘에 관한 연구 (A Study on the Characteristics of Surface Degradation & Degradation-Mechanism in UV Treated FRP)

  • 이백수;임경범;나동근;정무영;정의남;유도현;이덕출
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 추계학술대회 논문집 학회본부 C
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    • pp.813-815
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    • 1998
  • In order to analyse the degradation process of epoxy/glass fiber for outdoor condition, FRP laminate was exposed to the wavelength of ultraviolet rays and evaluated by comparing contact angle, surface resistivity, surface potential decay, and ESCA spectrum respectively. Finally, We can conclude that the degradation phenomena on the surface of epoxy composites are dominated by the induction of ester and carboxyl groups.

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Phanerochaete chrysosporium의 고상발효를 통한 리그노셀룰로오즈 분해 및 당화 (Solid State Fermentation of Phanerochaete chrysosporium for Degradation and Saccharification of Lignocellulose)

  • ;이은광;윤현식
    • KSBB Journal
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    • 제32권2호
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    • pp.96-102
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    • 2017
  • The lignocellulose that is a major component of spent coffee ground was degraded and saccharified. To implement the spent coffee, after several pre-treatments, inoculation of Phanerochaete chrysosporium and solid-state fermentation were conducted. The optimal temperature of the enzymes (lignin peroxidase, manganese peroxidase, xylanase, laccase, and cellulase) for degradation of lignocellulose by P. chrysosporium was found. We also measured the maximum activity of enzymes (lignin peroxidase 0.15 IU/mL, manganese peroxidase 0.90 IU/mL, laccase 0.11 IU/mL, cellulase 5.87 IU/mL, carboxymethyl cellulase 9.52 IU/mL, xylanase 1.16 IU/mL) used for the process. As a result, 4.73 mg/mL of reduced sugar was obtained and 61.02% of lignin was degraded by solid state fermentation of P. chrysosporium on spent coffee ground.

Evaluation of Irradiated Oxidation of XLPE Based on Thermal and IR Reflection Properties

  • Ryu, Boo-Hyung;Lee, Chung;Kim, Ki-Yup
    • International Journal of Safety
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    • 제7권1호
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    • pp.10-14
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    • 2008
  • For evaluating the radiation degradation of cross-linked polyethylene (XLPE) cable insulation due to the irradiated oxidation, XLPE was irradiated with ${\gamma}$-ray. For each irradiated samples, TGA, DSC, FT-IR, and tensile tests were carried out. Regarding radiation degradation, oxidative process was predominant. TGA, DSC and FT-IR can be useful tools for evaluating the radiation degradation due to the irradiated oxidation because these analyses need only small amount of samples. The results of TGA, DSC and FTIR analyses showed the similar tendency for irradiated degradation. They can be useful tools for evaluating the oxidation of insulating material by non-destructive testing.

Hot-carrier 효과로 인한 MOSFET의 성능저하 및 동작수명 측정 (Hot-carrier Induced MOSFET Degradation and its Lifetime Measurement)

  • 김천수;김광수;김여환;김보우;이진효
    • 대한전자공학회논문지
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    • 제25권2호
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    • pp.182-187
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    • 1988
  • Hot carrier induced device degradation characteristics under DC bias stress have been investigated in n-MOSFETs with channel length of 1.2,1.8 um, and compared with those of LDD structure device with same channel length. Based on these results, the device lifetime in normal operating bias(Vgs=Vds=5V) is evaluated. The lifetimes of conventional and LDD n-MOSFET with channel length of 1.2 um are estimated about for 17 days and for 12 years, respectively. The degradation rate of LDD n-MOSFET under the same stress is the lowest at n-region implnatation dose of 2.5E15 cm-\ulcorner while the substrate current is the lowest at the dose of 1E13cm-\ulcorner Thses results show that the device degradation characteristics are basic measurement parameter to find optimum process conditions in LDD devices and evaluate a reliability of sub-micron device.

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복합 스트레스에 의한 비정질 실리콘 박막 트랜지스터에서의 가속열화 현상 연구 (A Study of the Acclerated Degradation Phenomena on th Amorphous Silicon Thin Film Transistors with Multiple Stress)

  • 이성규;오창호;김용상;박진석;한민구
    • 대한전기학회논문지
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    • 제43권7호
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    • pp.1121-1127
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    • 1994
  • The accelerated degradation phenomena in amorphous silicon thin film transistors due to both electrical stress and visible light illumination under the elevated temperature have been investigated systematically as a function of gate bias, light intensity, and stress time. It has been found that, in case of electrical stress, the thrshold voltage shifts of a-Si:H TFT's may be attributed to the defect creation process at the early stage, while the charge trapping phenomena may be dominant when the stressing periods exceed about 2 hours. It has been also observed that the degradation in the device characteristics of a-Si:H TFT's is accelerated due to multiple stress effects, where the defect creation mechanism may be more responsible for the degradation rather than the charge trapping mechanism.

Submicron MOSTransistor에서 Hot-Carrier에 의한 열화현상의 연구 (Hot-Carrier Induced Degradation in Submicron MOS Transistor)

  • 최병진;강광남
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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    • pp.469-472
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    • 1987
  • The hot-carrier induced degradation in very short-channel MOSFET was studied systematically. Under the traditional DC stress conditions, the threshold voltage shift (${\Delta}Vt$) and the transconductance degradation (${\Delta}Gm$/(Gmo-${\Delta}Gm$)) were confirmed to depend exponentially on the stress time and the dependency between the two parameters was proved to be linear. And the degradation due to the DC stress across gate and drain was studied. As the AC dynamic process is more realistic in actual device operation, the effects of dynamic stresses were studied.

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대형 터빈 발전기용 고정자 권선의 1000 thermal cycle 후 전기적 특성 변화 (Electrical Degradation of Stator Bars for Large Turbine Generator after 1000 Thermal Cycles)

  • 강명국;김태희;이재권
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2007년도 제38회 하계학술대회
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    • pp.975-976
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    • 2007
  • Thermal and mechanical stresses, caused by repetitive start and stop and load fluctuation during long time operation, on winding stator bars are one of the main causes for electrical degradation of insulating materials. To understand the degradation process, we manufactured bar specimens with the same processes that make generator winding stator bars and the specimens were subjected to various degrees of thermal cycling. Measurements of the insulation properties, such as dissipation factor, tip-up and partial discharge, for un-aged specimens and for specimens aged by thermal cycling at 50, 100, 250, 500 and 1000 thermal cycles were performed. Finally all specimens were tested to obtain electrical breakdown voltages. In this paper we present the data and electrical degradation analysis results obtained during this program.

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Electrical Analysis of Bottom Gate TFT with Novel Process Architecture

  • Pak, Sang-Hoon;Jeong, Tae-Hoon;Kim, Si-Joon;Kim, Kyung-Ho;Kim, Hyun-Jae
    • Journal of Information Display
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    • 제9권2호
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    • pp.5-8
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    • 2008
  • Bottom gate thin film transistors (TFTs) with microcrystalline and amorphous Si (a-Si) double active layers (DAL) were fabricated. Since the process of DAL TFTs can use that of conventional a-Si TFTs, these DAL TFT process has advantages, such as low cost, large substrate, and mass production capacity. In order to analyze the degradation characteristics in saturation region for driving TFTs of active matrix organic light emitting diode, three different dynamic stresses were applied to DAL TFTs and a-Si TFTs. The threshold voltage shift of DAL TFTs and a-Si TFTs during 10,000 second stress is 0.3V and 2V, respectively. DAL TFTs were more reliable than a-Si TFTs.