• Journal of Information Processing Systems
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• v.16 no.6
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• pp.1359-1371
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• 2020

In transmitting and receiving such a large amount of data, reliable data communication is crucial for normal operation of a device and to prevent abnormal operations caused by errors. Therefore, in this paper, it is assumed that an error correction code (ECC) that can detect and correct errors by itself is used in an environment where massive data is sequentially received. Because an embedded system has limited resources, such as a low-performance processor or a small memory, it requires efficient operation of applications. In this paper, we propose using an accelerated ECC-decoding technique with a graphics processing unit (GPU) built into the embedded system when receiving a large amount of data. In the matrix-vector multiplication that forms the Hamming code used as a function of the ECC operation, the matrix is expressed in compressed sparse row (CSR) format, and a sparse matrix-vector product is used. The multiplication operation is performed in the kernel of the GPU, and we also accelerate the Hamming code computation so that the ECC operation can be performed in parallel. The proposed technique is implemented with CUDA on a GPU-embedded target board, NVIDIA Jetson TX2, and compared with execution time of the CPU.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.99-102
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• 1998

As multimedia communication services have been widely spreading, the amount of video traffic is rapidly increasing in B-ISDN environment based on the ATM technology. The image quality of MPEG services is very sensitive to the cell losses in ATM network, since each cell contains information needed at decoding process. Since the number of cells in each frame of MPEG is variable, this video smoothing technology need to prepare a buffer for no overflow or underflow at the transmission, requires that some number of cells be taken to the buffer in client before the playback of video. To ensure the high quality image of video, the video smoothing is scheduled by a Group of Picture unit. In this paper, we then apply the theory to reds nightmare encoded in MPEG, and find minimum smoothing buffer size, initial buffer size. It can be used to study the smoothing of stored video.

• Korean Journal of Cognitive Science
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• v.4 no.2
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• pp.263-278
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• 1994

This paper proposes a way of decoding and translating some metaphorical use in a SL(Source Language). The process of metaphorical usage should be different from that of idiomatic expressions,which can be treated as a flat structure or chunks(cf.Lee(1985)[5],Yoon & Kim(1993)[7].The representation of metaphorical usage is approached with'M'in a separate dictionary with the extened meaning of property.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.417-422
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• 2010

When memory devices are exposed to space environments, they suffer various effects such as SEU(Single Event Upset). Memory systems for space applications are generally equipped with error detection and correction(EDAC) logics against SEUs. In this paper, several error detection and correction codes - RS(10,8) code, (7,4) Hamming code and (16,8) code - are analyzed and compared with each other. Each code is implemented using VHDL and its performances(encoding/decoding speed, required memory size) are compared. Also the failure probability equation of each EDAC code is derived, and the probability value is analyzed for various occurrence rates of SEUs which the STSAT-3 possibly suffers. Finally, the EDAC algorithm for STSAT-3 is determined based on the comparison results.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.11b
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• pp.1631-1634
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• 2002

멀티미디어 서버는 클라이언트가 요청한 멀티미디어 데이터 스트림을 효율적으로 제공하기 위해 사용된다. 현재, 정보통신 기술의 발달로 인해 멀티미디어 서버는 멀티미디어 정보를 온라인으로 서비스 할 수 있게 되었다. 하지만 네트워크 상에서 발생하는 Packet Delay 에 때문에 서버에서 사용자에게 연속적이고 엄격한 실시간 제약이 있는 비디오 전송과 같은 멀티미디어 서비스를 제공하는 것은 매우 힘들다. 따라서, 본 논문에서는 서버에서 필요한 Packet 를 먼저 전송하여 Packet Delay 를 줄이는 방법을 제안하였다. MPEG-4 에서 오브젝트의 AU(Access Unit)들의 디코딩 시간을 표시하는 DTS(Decoding Time Stamp)를 참조하여 생성된 Deadline threshold 를 기준으로 Deadline 이 가장 빠른 AU부터 전송하는 스케줄링 알고리즘을 이용하여 MPEC-4 미디어 오브젝트를 스트리밍한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.533-536
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• 2005

MAP algorithm is known for optimal decoding algorithm of Turbo codes, but it has very large computational complexity and delay. Generally log-MAP algorithm is used in order to overcome the defect. In this paper we propose modified scheme of the state metric calculation block which can improve the computation speed in log-MAP decoder and simple linear offset unit without using LUT. The simulation results show that the operation speed of the proposed scheme is improved as compared with that of the past scheme.

• Journal of the Korean Institute of Intelligent Systems
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• v.18 no.3
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• pp.323-328
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• 2008

This paper presents a Digital Signal Processor achieving high through-put for both decision intensive and computation intensive tasks. The proposed processor employees a multiplier, two ALU and load/store. Unit as operational units. Those four units are controlled and works parallel by superscalar control scheme, which is different from prior DSP architecture. The performance evaluation was done by implementing AC-3 decoding algorithm and 37.8% improvement was achieved. This study is valuable especially for the consumer electronics applications, which require very low cost.

• Journal of Information Processing Systems
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• v.19 no.1
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• pp.98-108
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• 2023

This paper is an attempt to design segmentation method based on fully convolutional networks (FCN) and attention mechanism. The first five layers of the Visual Geometry Group (VGG) 16 network serve as the coding part in the semantic segmentation network structure with the convolutional layer used to replace pooling to reduce loss of image feature extraction information. The up-sampling and deconvolution unit of the FCN is then used as the decoding part in the semantic segmentation network. In the deconvolution process, the skip structure is used to fuse different levels of information and the attention mechanism is incorporated to reduce accuracy loss. Finally, the segmentation results are obtained through pixel layer classification. The results show that our method outperforms the comparison methods in mean pixel accuracy (MPA) and mean intersection over union (MIOU).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.6
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• pp.1409-1418
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• 1998

The recent audio CODEC(Coding/Decoding) algorithms are complex of several coding techniques, and can be divided into DSP tasks, controller tasks and mixed tasks. The traditional DSP processor has been designed for fast processing of DSP tasks only, but not for controller and mixed tasks. This paper presents a new architecture that achieves high throughput on both controller and mixed tasks of such algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates four algorithms while maintaining high performance for DSP tasks. The proposed processor, YSP-3, operates functional units (Multiplier, two ALUs, Load/Store Unit) in parallel via 4-issue super-scalar instruction structure. The performance evaluation of YSP-3 has been done through the implementation of the several DSP algorithms and the part of the AC-3 decoding algorithms.