• The Journal of the Convergence on Culture Technology
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• v.7 no.3
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• pp.565-570
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• 2021

A soft-decision decoding scheme of a channel code for correcting an error occurring in a receiver of a digital communication systems is proposed. A method for efficiently decoding by use of the linear and arithmetic structure of linear block codes is presented. In this way, the probability of decoding errors has been reduced. In addition, it is possible to reduce the complexity of decoding as well. Sufficient conditions for achieving optimal decoding has been derived. As a result, the sufficient conditions enable efficient search for candidate codewords. With the proposed decoding scheme, we can effectively perform the decoding while lowering the block error probability.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.2A
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• pp.195-202
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• 2007

A differential space-frequency block code - orthogonal frequency division multiplexing (SFBC-OFDM) scheme as a multiple-input multiple-output (MIMO) transmission technique for next-generation digital multimedia broadcasting (DMB) is proposed in this paper. A linear decoding method for differential SFBC, which performs comparably to the ML decoding method, is derived for the cases of two or four transmit antennas. A simple table lookup method is proposed to improve the efficiency of the encoding/decoding process of DSFBC for the case of non-constant modulus constellations. A DMB MIMO channel model, developed by extending the 3GPP MIMO model to fit DMB environments, is used to compare BER performances of differential space block code schemes for various channel environments. Simulation results show that the differential SFBC-16QAM scheme using either four transmit antennas with one receive antenna or two transmit antennas with two receive antennas achieves a performance gain of 12dB than that of the conventional DQPSK scheme, even with a data rate twice faster.

• ETRI Journal
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• v.36 no.4
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• pp.564-571
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• 2014

Sphere decoding (SD) for multiple-input and multiple-output systems is a well-recognized approach for achieving near-maximum likelihood performance with reduced complexity. SD is a tree search process, whereby a large number of nodes can be searched in an effort to find an estimation of a transmitted symbol vector. In this paper, a simple and generalized approach called layer pruning is proposed to achieve complexity reduction in SD. Pruning a layer from a search process reduces the total number of nodes in a sphere search. The symbols corresponding to the pruned layer are obtained by adopting a QRM-MLD receiver. Simulation results show that the proposed method reduces the number of nodes to be searched for decoding the transmitted symbols by maintaining negligible performance loss. The proposed technique reduces the complexity by 35% to 42% in the low and medium signal-to-noise ratio regime. To demonstrate the potential of our method, we compare the results with another well-known method - namely, probabilistic tree pruning SD.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.12-18
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• 1993

We have proposed a soft-decision decoding method for block codes. With careful examinations of the first hard-decision decoded results, The candidate codewords are efficiently searched for. Thus, we can reduce the decoding complexity (the number of hard-decision decodings) and lower the block error probability. Computer simulation results are presented for the (23,12) Golay code. They show that the decoding complexity is considerably reduced and the block error probability is close to that of the maximum likelihood decoder.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.11 no.4
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• pp.1987-2001
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• 2017

Low-density parity-check (LDPC) codes have attracted a great attention because of their excellent error correction capability with reasonably low decoding complexity. Among decoding algorithms for LDPC codes, the min-sum (MS) algorithm and its modified versions have been widely adopted due to their high efficiency in hardware implementation. In this paper, a self-adaptive MS algorithm using the difference of the first two minima is proposed for faster decoding speed and lower power consumption. Finding the first two minima is an important operation when MS-based LDPC decoders are implemented in hardware, and the found minima are often compressed using the difference of the two values to reduce interconnection complexity and memory usage. It is found that, when these difference values are bounded, decoding is not successfully terminated. Thus, the proposed method dynamically decides whether the termination-checking step will be carried out based on the difference in the two found minima. The simulation results show that the decoding speed is improved by 7%, and the power consumption is reduced by 16.34% by skipping unnecessary steps in the unsuccessful iteration without any loss in error correction performance. In addition, the synthesis results show that the hardware overhead for the proposed method is negligible.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.47 no.6
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• pp.66-74
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• 2010

Recently distributed video coding (DVC) is spotlighted for the environment which has restriction in computing resource at encoder. Wyner-Ziv (WZ) coding is a representative scheme of DVC. The WZ encoder independently encodes key frame and WZ frame respectively by conventional intra coding and channel code. WZ decoder generates side information from reconstructed two key frames (t-1, t+1) based on temporal correlation. The side information is regarded as a noisy version of original WZ frame. Virtual channel noise can be removed by channel decoding process. So the performance of WZ coding greatly depends on the performance of channel code. Among existing channel codes, Turbo code and LDPC code have the most powerful error correction capability. These channel codes use stochastically iterative decoding process. However the iterative decoding process is quite time-consuming, so complexity of WZ decoder is considerably increased. Analysis of the complexity of LPDCA with real video data shows that the portion of complexity of LDPCA decoding is higher than 60% in total WZ decoding complexity. Using the HDA (Hard Decision Aided) method proposed in channel code area, channel decoding complexity can be much reduced. But considerable RD performance loss is possible according to different thresholds and its proper value is different for each sequence. In this paper, we propose an adaptive HDA method which sets up a proper threshold according to sequence. The proposed method shows about 62% and 32% of time saving, respectively in LDPCA and WZ decoding process, while RD performance is not that decreased.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.249-255
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• 2007

In general, a large amount of the memory accesses are required for the CAVLC decoding in H.264/AVC. It is a serious problem for the applications such as a DMB and videophone services because the considerable power is consumed for accessing the memory. In order to solve this problem, we propose an efficient decoding method for the coeff-token which is one of the syntax elements of CAVLC. In this paper, the variable length code table is re-designed with the new codewords which are defined by investigating the architecture of the conventional codeword for the coeff_token element. A new coeff_token decoding method is developed based on the suggested table. The simulation results show that the proposed algorithm achieves an approximately 85% memory access saving without video-quality degradation, compared to the conventional CAVLC decoding.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1073-1081
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• 2005

This paper describes a 3.3 V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method. Most of Dfh converters with hiか speed current drive are an architecture choosing current switch cell, column, row decoding method but this decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. The designed D/A converter with an active chip area of $0.953\;mm^2$ is fabricated by using a 0.35um process. The simulation data shows that the rise/fall time, settling time, and INL/DNL are 1.92/2.1 ns, 12.71 ns, and a less than ${\pm}2.3/{\pm}58$ LSB, respectively. The power dissipation of the D/A converter with a single power supply of 3.3 V is about 224 mW.

• Journal of Korea Multimedia Society
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• v.17 no.8
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• pp.961-967
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• 2014

Raptor codes are a class of rateless codes originally designed for binary erasure channels. This paper presents a compact set of mathematical expressions for iterative soft decoding of raptor codes. In addition, an early termination scheme is employed, and it is embedded in a single algorithm with the formula. In the proposed algorithm, the performance is enhanced by adopting iterative decoding, both in each inner and outer code and in the concatenated code itself between the inner and outer codes. At the same time, the complexity is reduced by applying an efficient early termination scheme. Simulation results show that our proposed method can achieve better performance with reduced decoding complexity compared to the conventional schemes.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6C
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• pp.450-456
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• 2005

In this paper, we propose a high-speed turbo decoding algorithm and present results of its implementation. The latency caused by (de)interleaving and iterative decoding in conventional MAP turbo decoder can be dramatically reduced with the proposed scheme. The main cause of the time reduction is to use radix-4, center to top, and parallel decoding algorithm. The reduced latency makes it possible to use turbo decoder as a FEC scheme in the real-time wireless communication services. However the proposed scheme costs slight degradation in BER performance because the effective interleaver size in radix-4 is reduced to an half of that in conventional method. To ensure the time reduction, we implemented the proposed scheme on a FPGA chip and compared with conventional one in terms of decoding speed. The decoding speed of the proposed scheme is faster than conventional one at least by 5 times for a single iteration of turbo decoding.