• Title/Summary/Keyword: decoding delay

Search Result 128, Processing Time 0.027 seconds

Design of Interleaver using the MAP Algorithm Scheme in the Multi-User CDMA Communication System (다중 사용자 CDMA 통신 시스템에서 MAP 알고리즘 기법을 사용한 인터리버 설계)

  • Kim, Dong-Ok;Oh, Chung-Gyun
    • 한국정보통신설비학회:학술대회논문집
    • /
    • 2005.08a
    • /
    • pp.417-421
    • /
    • 2005
  • In the recent digital communication systems, the performance of Turbo Code using the error correction coding depends on the interleaver influencing the free distance determination and the recursive decoding algorithms that is executed in the turbo decoder. However, performance depends on the interleaver depth that needs many delays over the reception process. Moreover, turbo code has been known as the robust coding methods with the confidence over the fading channel. International Telecommunication Union(ITU) has recently adopted it as the standardization of the channel coding over the third generation mobile communications(IMT-2000). Therefore, in this paper, we proposed the interleaver that has the better performance than existing block interleaver, and modified turbo decoder that has the parallel concatenated structure using MAP algorithm. In the real-time voice and video service over third generation mobile communications, the performance of the proposed two methods was analyzed and compared with the existing methods by computer simulation in terms of reduced decoding delay using the variable decoding method over AWGN and fading channels for CDMA environments.

  • PDF

A Study on the Enhancement of Turbo Decoder Reducing Communication Error of a Fire Detection System for Marine Vessels (선박용 화재탐지장치의 통신 에러를 감소시키기 위한 수정된 터보코딩 알고리즘 개발에 관한 연구)

  • 정병홍;최상학;오종환;김경식
    • Journal of Advanced Marine Engineering and Technology
    • /
    • v.25 no.2
    • /
    • pp.375-382
    • /
    • 2001
  • In this study, an adapted Turbo Coding Algorithm for reducing communication error of a fire detection system for marine vessels, especially image transmission via power lone. Because it is necessary that this system communicate larger and faster than previous method, this study carried out enhancement a decoding speed by adaptation CRC with Turbo Code Algorithm, improvement of metric method, and reduction of decoding delay by using of Center-to-Top method. And the results are as follows: (1) Confirmed that a Turbo Code is so useful methods for reducing communication error in lots of noise environments. (2)Proposed technology in this study speed increasing method of Turbo Coding Algorithm proves 2 times faster than normal Turbo Code and communication error reducing as well in the board made by VHDL software & chips ALTERA company.

  • PDF

Transcoding Algorithm for SMV and G.723.1 Vocoders via Direct Parameter Transformation (SMV와 G.723.1 음성부호화기를 위한 파라미터 직접 변환 방식의 상호부호화 알고리듬)

  • 서성호;장달원;이선일;유창동
    • Proceedings of the IEEK Conference
    • /
    • 2003.07e
    • /
    • pp.2228-2231
    • /
    • 2003
  • In this paper, a transcoding algorithm for the Selectable Mode Vocoder (SMV) and the G.723.1 speech coder via direct parameter transformation is proposed. In contrast to the conventional tandem transcoding algorithm, the proposed algorithm converts the parameters of one coder to the Other Without going through the decoding md encoding process. The proposed algorithm is composed of four parts: the parameter decoding, line spectral pair (LSP) conversion, pitch period conversion, excitation conversion and rate selection. The evaluation results show that the proposed algorithm achieves equivalent speech quality to that of tandem transcoding with reduced computational complexity and delay.

  • PDF

High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

  • Byun, Wooseok;Kim, Hyeji;Kim, Ji-Hoon
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.14 no.4
    • /
    • pp.407-418
    • /
    • 2014
  • As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)-based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

Implementation of Efficient Channel Decoder for WiBro System (WiBro 시스템을 위한 효율적인 구조의 채널 복호화기 구현)

  • Kim, Jang-Hun;Han, Chul-Hee
    • Proceedings of the IEEK Conference
    • /
    • 2007.07a
    • /
    • pp.177-178
    • /
    • 2007
  • WiBro system provides reliable broadband communication services for mobile and portable subcribers. It allows interference-free reception under the conditions of multipath propagation and transmission errors. Thus, powerful channel-error correction ability Is required. CC/CTC Decoder which Is mandatory for WiBro system needs lots of computations for real-time operation. So, it is desired to design a CC/CTC Decoder having highly optimized hardware scheme for low latency operation under high data rates. This paper proposes an efficient CC/CTC Decoder structure for high data rate WiBro system. Particularly, the proposed CTC Decoder architecture reduces decoding delay by applying pipelining and multiple decoding blocks. Simulation results show that reduction of about 80% of processing time is enabled with the proposed CC/CTC Decoder despite of increase in are.

  • PDF

Performance Analysis of MAP Algorithm by Robust Equalization Techniques in Nongaussian Noise Channel (비가우시안 잡음 채널에서 Robust 등화기법을 이용한 터보 부호의 MAP 알고리즘 성능분석)

  • 소성열
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.25 no.9A
    • /
    • pp.1290-1298
    • /
    • 2000
  • Turbo Code decoder is an iterate decoding technology, which extracts extrinsic information from the bit to be decoded by calculating both forward and backward metrics, and uses the information to the next decoding step Turbo Code shows excellent performance, approaching Shannon Limit at the view of BER, when the size of Interleaver is big and iterate decoding is run enough. But it has the problems which are increased complexity and delay and difficulty of real-time processing due to Interleaver and iterate decoding. In this paper, it is analyzed that MAP(maximum a posteriori) algorithm which is used as one of Turbo Code decoding, and the factor which determines its performance. MAP algorithm proceeds iterate decoding by determining soft decision value through the environment and transition probability between all adjacent bits and received symbols. Therefore, to improve the performance of MAP algorithm, the trust between adjacent received symbols must be ensured. However, MAP algorithm itself, can not do any action for ensuring so the conclusion is that it is needed more algorithm, so to decrease iterate decoding. Consequently, MAP algorithm and Turbo Code performance are analyzed in the nongaussian channel applying Robust equalization technique in order to input more trusted information into MAP algorithm for the received symbols.

  • PDF

Effects of LDPCA Frame Size for Parity Bit Estimation Methods in Fast Distributed Video Decoding Scheme (고속 분산 비디오 복호화 기법에서 패리티 비트 예측방식에 대한 LDPCA 프레임 크기 효과)

  • Kim, Man-Jae;Kim, Jin-Soo
    • Journal of the Korea Institute of Information and Communication Engineering
    • /
    • v.16 no.8
    • /
    • pp.1675-1685
    • /
    • 2012
  • DVC (Distributed Video Coding) technique plays an essential role in providing low-complexity video encoder. But, in order to achieve the better rate-distortion performances, most DVC systems need feedback channel for parity bit control. This causes the DVC-based system to have high decoding latency and becomes as one of the most critical problems to overcome for a real implementation. In order to overcome this problem and to accelerate the commercialization of the DVC applications, this paper analyzes an effect of LDPCA frame size for adaptive LDPCA frame-based parity bit request estimations. First, this paper presents the LDPCA segmentation method in pixel-domain and explains the temporal-based bit request estimation method and the spatial-based bit request estimation method using the statistical characteristics between adjacent LDPCA frames. Through computer simulations, it is shown that the better performance and fast decoding is observed specially when the LDPCA frame size is 3168 in QCIF resolution.

A FPGA Design of High Speed LDPC Decoder Based on HSS (HSS 기반의 고속 LDPC 복호기 FPGA 설계)

  • Kim, Min-Hyuk;Park, Tae-Doo;Jung, Ji-Won
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
    • /
    • v.23 no.11
    • /
    • pp.1248-1255
    • /
    • 2012
  • LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

Rotational Drive-Versus-Quality and Video Compression-Versus-Delay Analysis for Multi-Channel Video Streaming System on Ground Combat Vehicles (지상 전투 차량을 위한 다채널 영상 스트리밍 시스템의 회전 구동 대비 품질과 압축 대비 지연 분석)

  • Yun, Jihyeok;Cho, Younggeol;Chang, HyeMin
    • Journal of the Korea Institute of Military Science and Technology
    • /
    • v.24 no.1
    • /
    • pp.31-40
    • /
    • 2021
  • The multi-channel video streaming system is an essential device for future ground combat vehicles. For the system, the application of digital interfaces is required instead of the direct analog method to support selectable multiple channels. However, due to the characteristics of the digital interfaces that require en/decoding and signal conversion, the system should support the ability to adapt to quality and delay requirements depending on how video data is utilized. To support addressed issue, this study designs and emulates the multi-channel compressed-video streaming system of ground combat vehicle's fire control system based on commercial standards. Using the system, this study analyzes the quality of video according to the rotational speed of the acquisition device and Glass-to-Glass (G2G) delay between video acquisition and display devices according to video compression rates. Through these experiments and analysis, this paper presents the design direction of the system having scalability on the latest technology while providing high-quality video data streaming flexibly.

Effetive delay reduced control method of iterative decoding for Turbo TCM (터보 TCM을 위한 지연 감소된 효율적인 반복 복호 제어 기법)

  • 김남경;김정수;김순영;이문호
    • Proceedings of the IEEK Conference
    • /
    • 2001.09a
    • /
    • pp.765-768
    • /
    • 2001
  • 본 논문에서는 터보 TCM(Turbo Trellis Coded Modulation)에서 복호기 입력 전에 수신데이터를 이용하여 SNR을 추정하고, SNR에 따라 요구하는 성능을 만족하는 반복 복호수를 적응적으로 복호기 앞단에서 미리 설정하는 반복복호 제어기법을 제안한다. 성능분석결과 최대 반복 복호를 수행했을 때와 비교하여 성능 감소 없이 평균 반복 복호수를 줄일 수 있었다. 따라서 제안구조는 터보 TCM의 복호화 과정에서 문제점 중 하나인 복호 계산량과 지연을 성능 저하 없이 효율적으로 감소시킬 수 있다.

  • PDF