• Journal of the Korea Institute of Military Science and Technology
• /
• v.15 no.1
• /
• pp.46-56
• /
• 2012

Traitor Tracing schemes are broadcast encryption systems where at least one of the traitors who were implicated in the construction of a pirate decoder can be traced. This traceability is required in various contents delivery system like satellite broadcast, DMB, pay-TV, DVD and so on. In this paper, we propose a public key traitor tracing scheme with key-update method. If the system manager can update a secret key which is stored in an authorized decode, it makes a pirate decoder useless by updating a secret key A pirate decoder which cannot update a secret key does not decrypt contents in next session or during tracing a traitor, this scheme has merits which will make a pirate decoder useless, therefore this scheme raises the security to a higher level.

• Journal of information and communication convergence engineering
• /
• v.1 no.4
• /
• pp.177-182
• /
• 2003

Conventional multilayer feedforward artificial neural networks are very effective in dealing with spatial problems. To deal with problems with time dependency, some kinds of memory have to be built in the processing algorithm. In this paper we show how the newly proposed Serial Input Neuron (SIN) convolutional decoders can be derived. As an example, we derive the SIN decoder for rate code with constraint length 3. The SIN is tested in Gaussian channel and the results are compared to the results of the optimal Viterbi decoder. A SIN approach to decode convolutional codes is presented. No supervision is required. The decoder lends itself to pleasing implementations in hardware and processing codes with high speed in a time. However, the speed of the current circuits may set limits to the codes used. With increasing speeds of the circuits in the future, the proposed technique may become a tempting choice for decoding convolutional coding with long constraint lengths.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.1C
• /
• pp.8-13
• /
• 2011

In this paper, we show new method to find error locations of 2 eight bit symbol errors for 2 error correcting Reed-Solomon decoder. New design is much faster and has much simpler logic circuit than the former design method. This optimization was possible by partitioning the 8 bit operations into 4 bit arithgmatic and logic operations. This Reed Solomon decoder can be used for data protection of almost all digital communication and consumer electronic devices.

• The Journal of Information Technology
• /
• v.3 no.1
• /
• pp.29-36
• /
• 2000

Viterbi decoder is a maximum likelihood decoding method for convolution coding used in satellite and mobile communications. In this paper, a Viterbi decoder with constraint length of K=7, 3 bit soft decision and traceback depth of ${\Gamma}=96$ for convolution code is implemented using VHDL. The hardware size of designed decoder is reduced by 4 bit pre-traceback in the survivor memory.

• 제어로봇시스템학회:학술대회논문집
• /
• 2002.10a
• /
• pp.89.1-89
• /
• 2002

Conventional multilayer feedforward artificial neural networks are very effective in dealing with spatial problems. To deal with problems with time dependency, some kinds of memory have to be built in the processing algorithm. In this paper we show how the newly proposed Serial Input Neuron (SIN) convolutional decoders can be derived. As an example, we derive the SIN decoder for \ulcornerrate code with constraint length 3. The SIN is tested in Gaussian channel and the results are compared to the results of the optimal Viterbi decoder. A SIN approach to decode convolutional codes is presented. No supervision is required. The decoder lends itself to pleasing implementations in hardware and processing...

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.281-284
• /
• 2000

This paper describes design of a (32, 28) Reed Solomon decoder for optical compact disk with double error detecting and correcting capability. A variety of error correction codes(ECCs) have been used in magnetic recordings, and optical recordings. Among the various types of ECCs, Reed Solomon(RS) codes has emerged as one the most important ones. The most complex circuit in the RS decoder is the part for finding the error location numbers by solving error location polynomial, and the circuit has great influence on overall decoder complexity. We use RAM based architecture with Euclid's algorithm, Chien search algorithm and Forney algorithm. We have developed VHDL model and peformed logic synthesis using the SYNOPSYS CAD tool. The total umber of gate is about 11,000 gates.

• Proceedings of the IEEK Conference
• /
• 2003.07b
• /
• pp.1173-1176
• /
• 2003

A high speed Viterbi decoder with a circularly connected 2-dimensional analog processing cell array is proposed. It has a 2-dimensional parallel processing structure in which an analog processing cell is placed at each node of a trellis diagram. The constraints' length of trellis diagram is connected circularly so that infinitively expanding trellis diagram is realized with the fixed size of circuits. The proposed Viterbi decoder has advantages in that it is operated with better performance of error correction, has a shorter latency and requires no path memories. The performance of error correction with the proposed Viterbi decoder is tested via the software simulation.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.34C no.11
• /
• pp.39-46
• /
• 1997

In this paper, we propose an area-efficient architecture of a reed-solomon (RS) decoder/encoder for digital VCRs. The new architecture of the decoder/encoder targeted to reduce the circit size and decoding latency has the following two features. First, area-efficeincy has been significantly improved by sharing a functional block for encoding, modified syndrome computation, and erasure locator polynomial evaluation. Second, modified euclid's algorithms has been implemented by using a new architecture. Experimental results have showed that the decoder/encoder designed by using the proposed method has been implemented with 25% smaller sie over straight forware implementation based on the conventional method [1] and the decoding latency has been reduced.

• Proceedings of the KSPS conference
• /
• 2006.05a
• /
• pp.89-93
• /
• 2006

This paper presents ETRI broadcast news speech recognition system. There are two major issues on the broadcast news speech recognition: 1) real-time processing and 2) out-of-vocabulary handling. For real-time processing, we devised the dual decoder architecture. The input speech signal is segmented based on the long-pause between utterances, and each decoder processes the speech segment alternatively. One decoder can start to recognize the current speech segment without waiting for the other decoder to recognize the previous speech segment completely. Thus, the processing delay is not accumulated. For out-of-vocabulary handling, we updated both the vocabulary and the language model, based on the recent news articles on the internet. By updating the language model as well as the vocabulary, we can improve the performance up to 17.2% ERR.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.9
• /
• pp.18-25
• /
• 1994

Previously. TCM decoder has been using the Viterbi algorithm that was complex. In order to reduce the complexity of decoder. we proposed the “modified decoding algorithm using the path back method” and the modified decoding algorithm which extends the previous decoding algorithm to be able to applied to TCM decoder in this paper. On the gaussian and impulsive noise channel. Monte-Carlo simulation is used for analyzing the TCM performance and proving the efficiency of proposed decoding algorithm.