• Title/Summary/Keyword: decimation

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Mesh Decimation for Polygon Rendering Based Real-Time 3-Axis NC Milling Simulation (실시간 3축 NC 밀링 시뮬레이션을 위한 메쉬 간략화 방법)

  • Joo, S.W.;Lee, S.H.;Park, K.H.
    • Korean Journal of Computational Design and Engineering
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    • v.5 no.4
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    • pp.347-358
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    • 2000
  • The view dependency of typical spatial-partitioning based NC simulation methods is overcome by polygon rendering technique that generates polygons to represent the workpiece, thus enabling dynamic viewing transformations without reconstruction of the entire data structure. However, the polygon rendering technique still has difficulty in realizing real-time simulation due to unsatisfactory performance of current graphics devices. Therefore, it is necessary to develop a mesh decimation method that enables rapid rendering without loss of display quality. In this paper. we proposed a new mesh decimation algorithm thor a workpiece whose shape varies dynamically. In this algorithm, the 2-map data thor a given workpiece is divided into several regions, and a triangular mesh is constructed for each region first. Then, if any region it cut by the tool, its mesh is regenerated and decimated again. Since the range of mesh decimation is confined to a few regions, the reduced polygons for rendering can be obtained rapidly. Our method enables the polygon-rendering based NC simulation to be applied to the computers equipped with a wider range of graphics cards.

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Decimation Chain Modeling for Dual-Band Radio Receiver and Its Operation for Continuous Packet Connectivity

  • Park, Chester Sungchung;Park, Sungkyung
    • Journal of information and communication convergence engineering
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    • v.13 no.4
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    • pp.235-240
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    • 2015
  • A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

3D data Compression by Modulating Function Based Decimation (변조함수를 이용한 decimation기법에 의한 3D 데이터 압축)

  • Yang, Hun-Gi;Lee, Seung-Hyeon;Gang, Bong-Sun
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.5
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    • pp.16-22
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    • 2000
  • This paper presents a compression algorithm applicable for transmitting a HPO hologram data. The proposed algorithm exploits a modulating function to compress the bandwidth of the hologram pattern, resulting in decimation due to relaxed Nyquist sampling constraints. At the receiver, the compressed data will be interpolated and compensated via being divided by the modulating function. We also present compression rate and analyze the resolution of a reconstructed image and the periodicity of harmonic interferences. Finally, we shows the validity of the proposed algorithm by simulation where a reconstructed image from undersampled data is compared with a reconstructed image obtained through decimatioin by modulating function, interpolation and compensation.

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Low-Power Decimation Filter Using Approximate Processing with Control of Error in CSD Representation (CSD 표현의 오차를 이용한 Approximate Processing과 이를 이용한 저전력 Decimation Filter의 설계)

  • 양영모;김영우;김수원
    • Proceedings of the IEEK Conference
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    • 1999.11a
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    • pp.236-239
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    • 1999
  • This paper describes a low-power design of decimation filter. To reduce power consumption, an approximate processing method which controls the error in canonic signed digit(CSD) coefficients is proposed. The CSD representation reduces the number of operations by representing multiplications with add and shift operations. The proposed method further reduces the number of operations by controlling the error of CSD coefficient. Processor type architecture is used to implement the proposed method. Simulation result shows that the number of operations is reduced to 56%, 35% and 10% at each approximated filter level.

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The Convergence Speed Enhancement using a Cosine Modulated Filter Banks and a Decimation Technique (코사인 변조된 필터 뱅크와 Decimation을 이용한 수렴 속도 성능 개선)

  • Choi Chang-Kwon;Cho Byung-Mo
    • Proceedings of the Acoustical Society of Korea Conference
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    • autumn
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    • pp.193-196
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    • 1999
  • 본 논문은 음향 임펄스를 모델링하는데 코사인 변조된 필터 뱅크와 Decimation을 이용하여 수렴 속도를 개선하는 방법을 제안하고 이를 잡음제거에 응용하였다. 제안된 구조는 입력신호를 필터뱅크를 이용하여 각 서브밴드로 분할한 후 필터 입력신호의 고유벡터의 최대값과 최소값의 비를 줄이고 필터의 탭수를 줄이기 위해서 decimation을 행한다. 그리고 서브밴드대역의 샘플링 주파수를 낮추어 신호 스펙트럼을 확장시켜 이를 적응필터에 입력하여 수렴속도를 향상시켰다. 실험 결과, Colored잡음의 경우 LMS 알고리즘보다 제안된 방법이 MSE(Mean Square Error)는 좋지는 않았다. 실제 음향시스템의 모델링에는 거의 같은 MSE을 갖으며, 수렴 속도에는 모두 빠른 성능을 보였으며, 이를 음질향상에 적용하여 향상된 음질을 얻을 수 있었다.

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Low-power Butterfly Structure for DIT Radix-4 FFT Implementation (DIT Radix-4 FFT 구현을 위한 저전력 Butterfly 구조)

  • Jang, Young-Beom;Lee, Sang-Woo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.38A no.12
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    • pp.1145-1147
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    • 2013
  • There are two FFT(Fast Fourier Transform) algorithms, which are DIT(Decimation-In-Time) and DIF(Decimation-In- Frequency). Even the DIF algorithm is more widely used because of its various implementation architectures, the DIT structures have not been investigated. In this paper, the DIT Radix-4 algorithm is derived and its efficient butterfly structure is proposed for SoC(System on a Chip) implementation.

System indentification using multiple decimation method and design of PID-ATC

  • Byun, Hwang-Woo;Moon, Joon-Ho;Lee, In-Hee;Lee, Un-Cheol;Kim, Lark-Kyo;Nam, Moon-Hyon
    • 제어로봇시스템학회:학술대회논문집
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    • 1994.10a
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    • pp.682-688
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    • 1994
  • LSM(Least-Squares Method) has inherent limitation that precise system identification over wide frequency band is difficult especially at low frequency hand. In this paper we propose to use decimation, a spectrum analysis method widely used in signal processing. The merits of decimation are the flexibility of selection of the frequency hand concerned and the function of LPF(Low Pass Filter). In this paper, frequency-domain is divided into separate frequency bands which will be combined into full frequency-domain by using MDM(Multiple Decimation Method). In this way, free selection of sampling frequency for each hand is possible and the low frequency oscillation modes of LSM are avoided.

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Pixel decimation for block motion vector estimation (블록 움직임 벡터의 검출을 위한 화소 간축 방법에 대한 연구)

  • Lee, Young;Park, Gwi-Tae
    • Journal of the Korean Institute of Telematics and Electronics S
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    • v.34S no.9
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    • pp.91-98
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    • 1997
  • In this paper, a new pixel decimation algorithm for the estimation of motion vector is proposed. In traditional methods, the computational cost can be reduced since only part of the pixels are used for motion vector calculation. But these methods limits the accuracy ofmotion vector because of the same reason. We derive a selection criteria of subsampled pixels that can reduce the probablity of false motion vector detection based on stochastic point of view. By using this criteria, a new pixel decimation algorithm that can reduce the prediction error with similar computational cost is presented. The simulation results applied to standard images haveshown that the proposed algorithm has less mean absolute prediction error than conventional pixel decimation algorithm.

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Multi-rate Non-recursive Architecture for Cascaded Integrator-Comb Decimation Filters with an Arbitrary Factor (임의의 인수를 갖는 cascaded Integrator-Comb 데시메이션 필터의 Multi-rte Non-recursive 아키텍처)

  • 장영범
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.25 no.10B
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    • pp.1785-1792
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    • 2000
  • In this paper multi-rate non-recursive architecture for CIC(Cascaded Integrator-Comb) decimation filters with an arbitrary factor is proposed. The CIC filters are widely used in high speed wireless communication systems since they have multiplier-less and multi-rate low-power structure. Even conventional non-recursive CIC structure is multi-rate this architecture can be structured only in case of M-th power-of-two decimation factor. This paper proposes that muli-rate non-recursive CIC architecture can be structured with an any decimation factor of product form. Power consumption of the proposed architecture is compared with that of the conventional non-recursion architecture.

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Design of three stage decimation filter using CSD code (CSD 코드를 사용한 3단 Decimation Filter 설계)

  • Byun, San-Ho;Ryu, Seong-Young;Choi, Young-Kil;Roh, Hyung-Dong;Lee, Hyun-Tae;Kang, Kyoung-Sik;Roh, Jeong-Jin
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.511-512
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    • 2006
  • Three stage(CIC-FIR-FIR) decimation filter in delta-sigma A/D converter for audio is designed. A canonical signed digit(CSD) code method is used to minimize area of multipliers. This filter is designed in 0.25um CMOS process and incorporates $1.36\;mm^2$ of active area. Measured results show that this decimation filter is suitable for digital audio A/D converters.

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