• 한국CDE학회논문집
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• 제5권4호
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• pp.347-358
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• 2000

The view dependency of typical spatial-partitioning based NC simulation methods is overcome by polygon rendering technique that generates polygons to represent the workpiece, thus enabling dynamic viewing transformations without reconstruction of the entire data structure. However, the polygon rendering technique still has difficulty in realizing real-time simulation due to unsatisfactory performance of current graphics devices. Therefore, it is necessary to develop a mesh decimation method that enables rapid rendering without loss of display quality. In this paper. we proposed a new mesh decimation algorithm thor a workpiece whose shape varies dynamically. In this algorithm, the 2-map data thor a given workpiece is divided into several regions, and a triangular mesh is constructed for each region first. Then, if any region it cut by the tool, its mesh is regenerated and decimated again. Since the range of mesh decimation is confined to a few regions, the reduced polygons for rendering can be obtained rapidly. Our method enables the polygon-rendering based NC simulation to be applied to the computers equipped with a wider range of graphics cards.

• Journal of information and communication convergence engineering
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• 제13권4호
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• pp.235-240
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• 2015

A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.

• 대한전자공학회논문지SD
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• 제37권5호
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• pp.16-22
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• 2000

본 논문은 HPO 홀로그램의 산란패턴을 전송하는데 적용 가능한 데이터 압축 알고리즘을 제시한다. 제시된 알고리즘은 홀로그램 데이터를 decimation 하기 위해서 변조함수를 이용해서 홀로그램 패턴의 대역폭을 압축시킨 것으로 수신단에서 데이터 복원을 위해서 인터폴레이션 과정이 필요하다. 압축 알고리즘 및 압축률의 유도와 함께 수신단에서 영상이 복원될 때 복원영상의 해상도 및 고조파(harmonic) 간섭영상의 주기를 분석한다. 마지막으로 시뮬레이션을 통해서 undersampling된 홀로그램 패턴에 대해 직접 복원시킨 결과와 변조함수에 의한 decimation 및 인터폴레이션 과정을 거친 후 복원시킨 결과를 비교하여 제시된 방법의 타당성을 보인다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.236-239
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• 1999

This paper describes a low-power design of decimation filter. To reduce power consumption, an approximate processing method which controls the error in canonic signed digit(CSD) coefficients is proposed. The CSD representation reduces the number of operations by representing multiplications with add and shift operations. The proposed method further reduces the number of operations by controlling the error of CSD coefficient. Processor type architecture is used to implement the proposed method. Simulation result shows that the number of operations is reduced to 56%, 35% and 10% at each approximated filter level.

• 한국음향학회:학술대회논문집
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• 한국음향학회 1999년도 학술발표대회 논문집 제18권 2호
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• pp.193-196
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• 1999

본 논문은 음향 임펄스를 모델링하는데 코사인 변조된 필터 뱅크와 Decimation을 이용하여 수렴 속도를 개선하는 방법을 제안하고 이를 잡음제거에 응용하였다. 제안된 구조는 입력신호를 필터뱅크를 이용하여 각 서브밴드로 분할한 후 필터 입력신호의 고유벡터의 최대값과 최소값의 비를 줄이고 필터의 탭수를 줄이기 위해서 decimation을 행한다. 그리고 서브밴드대역의 샘플링 주파수를 낮추어 신호 스펙트럼을 확장시켜 이를 적응필터에 입력하여 수렴속도를 향상시켰다. 실험 결과, Colored잡음의 경우 LMS 알고리즘보다 제안된 방법이 MSE(Mean Square Error)는 좋지는 않았다. 실제 음향시스템의 모델링에는 거의 같은 MSE을 갖으며, 수렴 속도에는 모두 빠른 성능을 보였으며, 이를 음질향상에 적용하여 향상된 음질을 얻을 수 있었다.

• 한국통신학회논문지
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• 제38A권12호
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• pp.1145-1147
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• 2013

FFT(Fast Fourier Transform) 알고리즘에는 DIT(Decimation-In-Time)와 DIF(Decimation-In-Frequency)가 있다. DIF 알고리즘은 Radix-2/4/8 등의 다양한 종류와 그 구현 방법이 개발되어 사용되는데 반하여 DIT 알고리즘은 순차적인 출력을 낼 수 있는 장점에도 불구하고 다양한 구현방법이 연구되지 못하였다. 이 논문에서는 DIT Radix-4 알고리즘을 유도하며 반도체 구현을 위한 효율적인 butterfly 구조를 제안한다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1994년도 Proceedings of the Korea Automatic Control Conference, 9th (KACC) ; Taejeon, Korea; 17-20 Oct. 1994
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• pp.682-688
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• 1994

LSM(Least-Squares Method) has inherent limitation that precise system identification over wide frequency band is difficult especially at low frequency hand. In this paper we propose to use decimation, a spectrum analysis method widely used in signal processing. The merits of decimation are the flexibility of selection of the frequency hand concerned and the function of LPF(Low Pass Filter). In this paper, frequency-domain is divided into separate frequency bands which will be combined into full frequency-domain by using MDM(Multiple Decimation Method). In this way, free selection of sampling frequency for each hand is possible and the low frequency oscillation modes of LSM are avoided.

• 전자공학회논문지S
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• 제34S권9호
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• pp.91-98
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• 1997

In this paper, a new pixel decimation algorithm for the estimation of motion vector is proposed. In traditional methods, the computational cost can be reduced since only part of the pixels are used for motion vector calculation. But these methods limits the accuracy ofmotion vector because of the same reason. We derive a selection criteria of subsampled pixels that can reduce the probablity of false motion vector detection based on stochastic point of view. By using this criteria, a new pixel decimation algorithm that can reduce the prediction error with similar computational cost is presented. The simulation results applied to standard images haveshown that the proposed algorithm has less mean absolute prediction error than conventional pixel decimation algorithm.

• 한국통신학회논문지
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• 제25권10B호
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• pp.1785-1792
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• 2000

In this paper multi-rate non-recursive architecture for CIC(Cascaded Integrator-Comb) decimation filters with an arbitrary factor is proposed. The CIC filters are widely used in high speed wireless communication systems since they have multiplier-less and multi-rate low-power structure. Even conventional non-recursive CIC structure is multi-rate this architecture can be structured only in case of M-th power-of-two decimation factor. This paper proposes that muli-rate non-recursive CIC architecture can be structured with an any decimation factor of product form. Power consumption of the proposed architecture is compared with that of the conventional non-recursion architecture.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.511-512
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• 2006

Three stage(CIC-FIR-FIR) decimation filter in delta-sigma A/D converter for audio is designed. A canonical signed digit(CSD) code method is used to minimize area of multipliers. This filter is designed in 0.25um CMOS process and incorporates $1.36\;mm^2$ of active area. Measured results show that this decimation filter is suitable for digital audio A/D converters.