• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.7
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• pp.455-463
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• 2001

In this Paper, an approximate processing method is proposed and tested. The proposed method uses variable CSD (VCSD) coefficients which approximate filter stopband attenuation by controlling the precision of the CSD coefficient sets. A decimation filter for Audio Codec '97 specifications has been designed having processor architecture that consists of program/data memory, arithmetic unit, energy/level decision, and sinc filter blocks, and fabricated with 0.6${\mu}{\textrm}{m}$ CMOS sea-of-gate technology. For the combined two halfband FIR filters in decimation filter, the number of addition operations were reduced to 63.5%, 35.7%, and 13.9%, compared to worst-case which is not an adaptive one. Experimental results show that the total power reduction rate of the filter is varying from 3.8 % to 9.0 % with respect to worst-case. The proposed approximate processing method using variable CSD coefficients is readily applicable to various kinds of filters and suitable, especially, for the speech and audio applications, like oversampling ADCs and DACs, filter banks, voice/audio codecs, etc.

• Proceedings of the IEEK Conference
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• 2001.09a
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• pp.47-50
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• 2001

본 논문에서는 프레임 메모리를 줄이는 간이형 비디오 디코더의 다섯가지 알고리즘을 연구하여 성능을 비교한다. fixed-length ADPCM 기법을 적용하여 메모리를 줄이는 알고리즘과 수평 방향으로 decimation 하는 방법, 그리고 DCT 계수를 filtering 하는 방법을 구현하고 이보다 더 압축률을 높여서 수평 방향으로 decimation 하거나 DCT 계수를 filtering 하는 방법에 ADPCM 기법을 결합한다. 이렇게 함으로써 원래의 비디오 디코더 프레임 메모리의 25% 까지 메모리를 줄일 수가 있다. 메모리 크기를 줄이는 이점 이외에, 하나의 비디오 디코더 구조가 몇가지 압축 모드를 구성하므로 원하는 복잡도와 메모리 크기에 따라 응용이 자유롭다.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1045-1048
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• 1998

This paper proposes a efficient algorithm of letter-box converter using 4:3 decimation algorithm. To display 16:9 wide images on a 4:3 screen, there is need to convert the 16:9 wide images. The letter-box converter is designed with multiplierless architecture. We have modeled the letter-box converter in verilog-HDL and verified to show little difference between the original image and the converte image.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.4 no.4
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• pp.391-397
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• 2003

This paper is about the digital image decimation algorithm which generates a value of decimated element by an average of a target pixel value and a value of neighbor intelligible element to adaptively reflect the merits of ZOD method and FOD method on the decimated image. First, a target pixel located at the center of sliding window is selected, then the gradient amplitudes of its right neighbor pixel and its lower neighbor pixel are calculated using first order derivative operator respectively. Secondly, each gradient amplitude is divided by the summation result of two gradient amplitudes to generate each intelligible weight. Next, a value of neighbor intelligible element is obtained by adding a value of the right neighbor pixel times its intelligible weight to a value of the lower neighbor pixel times its intelligible weight. The decimated image can be acquired by applying the process repetitively to all pixels in input image which generates the value of decimated element by calculating the average of the target pixel value and the value of neighbor intelligible element.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.8
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• pp.5579-5585
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• 2015

In FFT(Fast Fourier Transform) implementation, DIT(Decimation-In-Time) and DIF (Decimation-In-Frequency) methods are mostly used. Among them, various DIF structures such as Radix-2/4/8 algorithm have been developed. Compared to the DIF, the DIT structures have not been investigated even though they have a big advantage producing a sequential output. In this paper, a butterfly structure for DIT Radix-8 algorithm is proposed. The proposed structure has smaller latency time because of Radix-8 algorithm in addition to the advantage of the sequential output. In case of 4096-point FFT implementation, the proposed structure has only 4 stages which shows the smaller latency time compared to the 12 stages of Radix-2 algorithm. The proposed butterfly can be used in FFT block required the sequential output and smaller latency time.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.6C
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• pp.777-784
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• 2004

In this paper, a new filter structure to improve frequency response characteristics in decimation filter using CIC(Cascaded Integrator-Comb) filters and half band filters is proposed. Conventional filters improve only passband characteristics, but we propose a new filter which can improve stop band and pass band characteristics simultaneously. Since proposed filter needs only two multiplication, additional implementation cost is not much. And overall linear phase characteristics are maintained since the proposed filter is also linear phase. Finally, filter coefficients quantization effects ate discussed after Verilog-HDL coding.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.388-390
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• 2006

This paper presents a hybrid SoC design for phase detection of single tone signal. The designed hybrid SoC is composed of three functional blocks, i.e., an analog to digital converter module, a phase detection module and a controller module. A design of the controller module is based on a 16-bit RISC architecture. An I/O interface and an LCD control interface for transmission and display of phase measurement values are included in the design of the controller module. A design of the phase detector is based on a recursive sliding-DFT. The recursive architecture effectively reduces the gate numbers required in the implementation of the module. The ADC module includes a single-bit second-order sigma-delta modulator and a digital decimation filter. The decimation filter is designed to give 98dB of SNR for the ADC. The effective resolution of the ADC is enhanced to 98dB of SNR by the incorporation of a pre FIR filter, a 2-stage cascaded integrator- comb(CIC) filter and a 30-tab FIR filter in the decimation. The hybrid SoC is verified in FPGA and implemented in 0.35 CMOS Technology.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.4
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• pp.1-8
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• 2010

In this paper, we propose a new gain optimization technique for Sigma-Delta A/D converters. In the proposed scheme, multiple gain set candidates showing maximum SNR in the modulator block are selected, and then multiple gain set candidates are investigated for minimum MSE in decimation block. Through CIC decimation filter simulation, it is shown that second SNR ranking candidate in modulation block is the best gain set.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.9
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• pp.31-38
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• 2009

In this paper, we propose new gain optimization method for Sigma-Delta A/D converters. First, in proposed method, the 10 candidates are selected through SNR maximization for Sigma-Delta modulator. After then, it is shown that optimum gains can be obtained through MSE calculation for CIC decimation filter. In the simulation, The proposed method has advantages which utilize SNR maximization for modulator and MSE minimization for CIC decimation later. The more candidates are chosen in SNR maximization for modulator, the better gains can be obtained in MSE minimization for CIC decimation filter.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.8
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• pp.1687-1694
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• 2011

In this paper, we propose the design procedure of a digital IF system for the OFDM based WLAN system and examine its performances. Along with the decision procedure of ADC sample rate, NCO frequency and the required decimation ratio, we show the decimation ratio is accomplished through the use of a CIC filter and a MHBF. We also show that the amplitude distortion occurred in the decimation filters can effectively be compensated by a ISOP filter and an additional FIR filter, which leads to the reduction of the overall hardware complexity. Finally, we examine the BER performance of the proposed system and compare it with a theoretical one that excludes filter non-linearities.