• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.31-40
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• 2009

This paper presents a design of a high performance DC-DC boost converter as a power module for SOC designs. It applied to this chip that reduced inductor and capacitor for integrating on a chip, and it operates with a switching frequency of 100MHz. It has reliability and stability in high switching frequency. The controller of DC-DC boost converter is designed by voltage-mode control method and compensated properly. The designed DC-DC converter is fabricated with the 0.18${\mu}m$ standard CMOS technology with a thick-gate oxide option. The overall die size is 8.14$mm^2$, and controller size is 1.15$mm^2$. The converter has the maximum efficiency over 76% for the output voltage of 4V and load current larger 300mA. The load regulation is 0.012% (0.5mV) for the load current change of 100mA.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.8
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• pp.24-31
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• 2008

Power converters are becoming an essential block in modem mobile multimedia application. This paper presents a high performance DC-DC buck converter for mobile applications. Controller of DC-DC buck converter is designed by current-mode control method. An current-mode DC-DC converter is implemented in a standard $0.18{\mu}m$ CMOS process, and the overall die size was $1.2mm^2$. The peak efficiency was 86 % with a switching frequency of $1\sim1.5MHz$ and a maximum load current of 400mA.

• Journal of IKEEE
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• v.17 no.3
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• pp.284-293
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• 2013

This paper describes a DC-DC boost converter for thermoelectric energy harvesting. The designed converter boosts the VDD through a start-up block from a low-output voltage of a thermoelectric device and the boosted VDD is used to operate the internal control block. When the VDD reaches a predefined value, a detector circuit makes the start-up block turn off to minimize current consumption. The final boosted VOUT is achieved by alternately operating the DC-DC converter for VDD and the main DC-DC converter for VOUT according to the comparator outputs. Simulation results shows that the designed converter generates 2.65V from an input voltage of 200mV and its maximum power efficiency is 63%. The area of the chip designed using a 0.35um CMOS process is $1.3mm{\times}0.7mm$ including pads.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.59-64
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• 2008

Recently, DC-DC choppers must be increased switching frequency in order to achieve a small size, a light weight and a low noise. However, the switches of chopper are subjected to high switching power losses and switching stresses. As a result of these, the chopper system bring on a low power efficiency. To improved these, this paper is studied on a new DC-DC chopper of high efficiency operated with soft switching(that is, zero current switching and zero voltage switching, ZVCS), of semiconductor switches using in chopper. The soft switching operation is applied to a partial resonant method that the switches operate at zero current of inductor and zero voltage of capacitor in resonant circuit. And the partial resonant circuit makes use of a inductor using step-up and a snubber capacitor, the circuit topology of chopper is simple. Some simulative results on computer and experimental results confirm the validity of analytical results of the DC-DC chopper.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.86-90
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• 2007

An efficient sensing scheme applicable to DC-DC converters is proposed. The output voltage of the DC-DC converter is fed back and converted to a current signal at the input terminal of the sensor to decide if it is in the tolerable range. The comparison is accomplished by a current push-pull action. With the embedded reference current in the sensor realized from the reference voltage. The advantages of the scheme lie in the fairly accurate and efficient implementation in terms of power consumption and chip size overhead compared with conventional voltage-mode schemes as the major parameter in converting voltage to current is determined by (W/L) aspect ratio of the core transistors. In this paper, a DC-DC converter of 5V output from battery range of 2.2V${\sim}$3.6V adopting the proposed sensing scheme is implemented in a 0.35um CMOS process to prove the validity of the scheme.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.852-855
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• 2012

A DC-DC converter for EEPROM IPs which perfom erasing by the FN (Fowler-Nordheim) tunneling and programming by the band-to-band tunneling is designed in this paper. For the DC-DC converter for EEPROM IPs using a low voltage of $1.5V{\pm}10%$ as the logic voltage, a scheme of using VRD (Read Voltage) instead of VDD is proposed to reduce the pumping stages and pumping capacitances of its charge pump circuit. VRD ($=3.1V{\pm}0.1V$) is a regulated voltage by a voltage regulator using an external voltage of 5V. The designed DC-DC converter outputs VPP (=8V) and VNN (=-8V) in the write mode.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.49 no.1
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• pp.57-63
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• 2012

In this paper, a switch sizing method is proposed in order to prevent the cross-regulation in the TM type SIDO DC-DC buck converter. In TM type SIDO DC-DC buck converter, a DCM operation is required. In the DCM operation, the inductor peak current is larger than that in the CCM. Because of the larger inductor peak current and the added switch resistance, the voltage drop is increased, resulting in possible cross-regulation. To solve this problem, the switch resistance must be considered in sizing the switch. To simplify the calculation of the resistance, the inductor current was replaced by the average load current. Using the proposed method, TM type SIDO DC-DC buck converter for camera module was designed to provide two independent supply voltage(2.8 V and 1.8 V). The designed circuit was fabricated in a standard $0.35{\mu}m$ CMOS process. At a switching frequency of 1 MHz and a load current of 200 mA, a power effciency of 80.7% was achieved.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.21 no.6
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• pp.55-64
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• 2007

This paper represents characteristics and design example of series loaded LCC type high frequency resonant DC-DC converter with variable parallel capacitor in the secondary side of inductive power transformer. In this converter, ZVS(zero voltage switching) technique is applied to reduce turn-off switching losses, and the applied converter used the PFM switching pattern to control output voltage. The operating characteristics of the proposed converter is analyzed using nomalized parameter such as switching frequency and load factor with varing the secondary parallel resonant capacitor. The results of analysis show the operating characteristics and design method of the proposed converter using characteristic values. And the proposed converter can be applied for the contactless power supply with linear transfer system such as dean room facilities of semiconductor and Flat Panel Display.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.207-217
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• 2010

Recently, the use of DC power increased due to the increased use of digital load. Power factor of input current decrease and input current harmonics increase, and conversion loss which is occurred in the AC / DC converter is a problem to provide the proper DC voltage to the device equipped with an internal AC / DC converter. Hybrid system supplies the AC power and DC power to AC load (motor load and the transformer load) and DC loads (computers, TV, LED fluorescent light) at the same time it supplies the renewable energy and utility energy taken power from Utility to user for improving the efficiency and renewable energy improvements in ease of use. This paper studies DC characteristics of traditional AC load for Hybrid distributions.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.6
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• pp.25-32
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• 2011

This paper proposes high efficiency current-mode DC-DC buck converter that are suitable for portable devices. The current-mode DC-DC buck converter using adjustable Dead-time control method improves the power efficiency 2~5%. The buck converter has been implemented with a standard 0.35${\mu}m$ CMOS process. The size of this chip is 0.97$mm^2$. The input range of the fabricated DC-DC buck converter is 2.5V~3.3V, and the output is 1.8V. The maximum loading current of the converter is 500mA and the peak efficiency is 93% at 200mA loads.