• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.10
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• pp.81-92
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• 1995

In this paper, we present a high-level synthesis system that generates area-efficient RT-level datapaths with multiport memories. The proposed scheduling algorithm assigns an operation to a specific control step such that maximal sharing of functional units can be achieved with minimal number of memory ports, while satisfying given constraints. We propose a measure of multiport memory cost, MAV (Multiple Access Variable) which is defined as a variable accessed at several control steps , and overall memory cost is reduced by equally distributing the MAVs throughout all the control steps. Experimental results show the effectiveness of the proposed algorithm. When compared with previous approaches for several benchmarks available from literature, the proposed algorithm generates the datapaths with less memory modules and interconnection structures by reflecting the memory cost in the scheduling process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.6A
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• pp.526-534
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• 2005

This paper presents the structure and function of the system which automatically generates embedded processor cores using the SMDL. Accepting processor description in the SDML, the proposed system generates the processor core, consisting of the pipelined datapath and memory modules together with their control unit. The generated cores support muti-cycle instructions for proper handling of memory accesses, and resolve pipeline hazards encountered in the pipelined processors. Experimental results show the functional accuracy of the generated cores.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1332-1344
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• 1996

This paper presents a pipelined floating point multiplier(FMUL) for superscalar microprocessors that conbines radix-16 recoding scheme based on signed-digit(SD) number system and new rouding and normalization scheme. The new rounding and normalization scheme enable the FMUL to compute sticky bit in parallel with multiple operation and elminate timing delay due to post-normalization. By expoliting SD radix-16 recoding scheme, we can achieves further reduction of silicon area and computation time. The FMUL can execute signle-precision or double-precision floating-point multiply operation through three-stage pipelined datapath and support IEEE standard 754. The algorithm andstructure of the designed multiplier have been successfully verified through Verilog HOL modeling and simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.5
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• pp.1345-1359
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• 1996

This paper presents a floating point arithmetic unit (FPAU) for supescalar microprocessor that executes fifteen operations such as addition, subtraction, data format converting, and compare operation using two pipelined arithmetic paths and new rounding and normalization scheme. By using two pipelined arithmetic paths, each aritchmetic operation can be assigned into appropriate arithmetic path which high speed operation is possible. The proposed normalization an rouding scheme enables the FPAU to execute roundig operation in parallel with normalization and to reduce timing delay of post-normalization. And by predicting leading one position of results using input operands, leading one detection(LOD) operation to normalize results in the conventional arithmetic unit can be eliminated. Because the FPAU can execuate fifteen single-precision or double-precision floating-point arithmetic operations through three-stage pipelined datapath and support IEEE standard 754, it has appropriate structure which can be ingegrated into superscalar microprocessor.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.597-598
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• 2008

In this paper, a sample design of I/O port of micro-processor using ODC(Output Don't Care) computation that is one of methods for Clock Gating applicable at the register transfer level(RTL). The ODC computation Method is applied at the point that estimate the value considering Don't Care Conditions from output of datapath to registers using clock in logic system. This paper also shows the results of reduce consumption power due to controlling clock that was supplied at registers. In Experimental results, ODC computation Method reduce power reductions of around 37.5%

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.5
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• pp.1-17
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• 1997

With the increasing performance and density of VLSI scircuits as well as the popularity of portable devices such as personal digital assitance, power consumption has emerged as an important issue in the design of electronic systems. Low power design techniqeus have been pursued at all design levels. However, it is more effective to attempt to reduce power dissipation at higher levels of abstraction which allow wider view. In this paper, we propose a simultaneous scheduling and binding scheme which increases the correlation between cosecutive inputs to an operation so that the switched capacitance of execution units is reduced in datapath-dominated circuits. The proposed method is implemented and integrated into the scheduling and assignment part of HYPER synthesis environment. Compared with original HYPER synthesis system, average power saving of 23.0% in execution units and 14.2% in the whole circuits, ar eobtained for a set of benchmark examples.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.381-384
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• 1999

In this paper, we addressed the problem of reducing the switching activity in pipeline datapath and proposed a solution. clock-gating method is a kind of practical technique for reducing switching activity in finite state machine. But, in the case that the target gated function unit has a pipeline structure, there is some spurious switching activity on each stage register group. This occur in early stage of every function enable cycle. In this paper we proposed a method to solve this problem. This method generates the enable signal to each pipeline stage to gate the clock feeding register group. Experimental results showed effective reduction of dynamic powers in pipeline circuits.

• The Journal of Information Technology
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• v.5 no.1
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• pp.133-142
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• 2002

This paper presents an efficient implementation of the linear window operator. I derived computational primitives based upon a block state space representation. The computational primitive can be implemented as a data path for a programmable processor, which can be used for the efficient implementation of a linear window operator. A multiprocessor architecture is presented for the realtime processing of a linear window operator. The architecture is designed based upon the data partitioning technique. Performance analysis for the various block size is provided.

• ETRI Journal
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• v.33 no.3
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• pp.466-469
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• 2011

As a fine-grained power gating method for achieving greater power savings, our approach takes advantage of the finite state machine with a datapath (FSMD) characteristic which shows sequential idleness among subcircuits. In an FSMD-based power gating, while only an active subcircuit is expected to be turned on, more subcircuits should be activated due to the power overhead. To reduce the number of missed opportunities for power savings, we deactivated some of the turned-on subcircuits by slowing the FSMD down and predicting its behavior. Our microprocessor experiments showed that the power savings are close to the upper bound.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.249-250
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• 2008

In this paper, we propose the single polycrystalline silicon flash EEPROM IC with a new structure which does not need the high voltage switching circuit. The design of high voltage switching circuits which are needed for the data program and erase, has been an obstacle to develop the single-poly EEPROM. Therefore, we has proposed the new cell structure which uses the low voltage switching circuits and has designed the full chip. A new single-poly EEPROM cell is designed and the full chip including the control block, the analog block, row decoder block, and the datapath block is designed. And the each block is verified by using the computer simulation. In addition, the full chip layout is performed.